# Anyone help me understand usrp fpga code fragment which count rssi

the code below is in sdr_lib/rssi.v I don’t understand especially this
line:

always @(posedge clock)
if(reset | ~enable)
else

On Wed, Aug 3, 2011 at 6:30 PM, Page J. [email protected]
wrote:

``````   rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
``````

[email protected]

It appears to be a clever way to implement a single pole IIR filter.
Josh?

If you recall an IIR is defined as y[n] = (1-alpha) * y[n-1] + x[n]

Since multiplier are expensive in hardware, lets use a multiples of two
so
you can bit shift, then add and subtract. In this case alpha is 2^-10

–Colby

Hi Colby,
I don’t understand why compute RSSI need an IIR filter? as I know the
can be compute
like that: (sample[0]*sample[0]+…sample[i]*sample[i]) / (i+1)

Regards!

Cheaper in hardware. You only need one adder.

Hi Colby,
I know cheaper in hardware, but now I don’t understand how using IIR
filter

On 08/04/2011 09:52 PM, Page J. wrote:

Hi Colby,
I know cheaper in hardware, but now I don’t understand how using IIR

The power estimate in a complex channel is computed as:

AVG(I2 + Q2)

An IIR filter is a simple way of approximating the AVG part of that
equation, and computing the
absolute value is another approximation for the I2 and Q2 part.
section that it essentially computes the absolute value.

Principal Investigator

On 08/04/2011 07:12 PM, Marcus D. Leech wrote:

On 08/04/2011 09:52 PM, Page J. wrote:

Hi Colby,
I know cheaper in hardware, but now I don’t understand how using IIR

Seems to me that the RSSI-in-FPGA stuff was not really fully baked,
function isn’t used by any higher-level functions in the USRP2/N2XXX
implementations.

It was never used. That rssi.v file is just there so people can ask
about it every few weeks. Its probably one of the least interesting
things in the library of verilog components.

On 08/04/2011 09:52 PM, Page J. wrote:

Hi Colby,
I know cheaper in hardware, but now I don’t understand how using IIR

Seems to me that the RSSI-in-FPGA stuff was not really fully baked,
function isn’t used by any higher-level functions in the USRP2/N2XXX
implementations.

I always compute the signal strength at the final channel bandwidth, in
the FPGA code seems to be running at the raw ADC bandwidth–which can
produce wildly
channel bandwidth.

Principal Investigator