Algorithm RSSI on FPGA

I’m working on RSSI value and reading mailing lists I have understood
how RSSI
is calculated. In the algorithm of RSSI in verilog alpha value is 2^-10
the shift is made on 10 bits. I want to change alpha value (decrease or
increase) but I don’t understand how I can change it in the algorithm in
verilog. Could you help me?

Thank you very much.


It’s very simple.

Take a look at the Verilog FPGA code:

I actually think it’s masking out 2^-11 by default.

See everywhere where it has [25:10] … this means that it is masking
out the bottom 11 bits (10,9,8…0). If you want it to be 2^-10, change
all the [25:10] to [25:9].

Then, rebuild.

  • George

I have read your answer but I have a doubt. If I change alpha value, for
putting 2^-10, according to me, it is not correct to change all [25:10]
[25:9] because writing

“over_count = over_count_int[25:9]” and “rssi = rssi_int[25:9]”

I lose MSB. Instead, if I want to change alpha value, for example 2^-13,
how can
I do?
I sent you my attached solution. In my solution, “input [4:0] alpha”
the shift which will do. Is correct my solution?

Thank you very much.