Advice on I/Q control using USRP

GNU Radio
1

Hi,

I want to control I/Q signal going through USRP by the
path of DEMOD->RX->FPGA->TX->MOD, quite similar to
what have been done by Jon Jacky in the following
presentation:

http://www.research.cornell.edu/KIC/events/MRFM2006/pdfs/Jacky%20talk/jacky-talk.html

The main different is that I’m going to use I/Q signal
from analogue DEMOD instead of doing the digital
demodulation.

I’ve been thinking about the easiest way on how to
achieve this aim. Do I need to program the FPGA using
Verilog or can I just get away with higher level
C++/Python code?

How about the delay for the processing, is it possible
to get less than 1 us delay?

Regards,
Shaiful Hashim,
Cardiff School of Engineering, UK

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2

On Tue, Apr 10, 2007 at 10:22:35AM -0700, Shaiful wrote:

from analogue DEMOD instead of doing the digital
demodulation.

I’ve been thinking about the easiest way on how to
achieve this aim. Do I need to program the FPGA using
Verilog or can I just get away with higher level
C++/Python code?

How about the delay for the processing, is it possible
to get less than 1 us delay?

To achieve 1us delay, you’ll need to keep all the signal processing on
the FPGA. We can’t get to the host in back in that time.

Eric