Would anyone be interested in an additional decimation stage after the
CIC and the halfband filters? The usable bandwidth is ~25-50% of the
actual post decimation sample rate, an additional decimation stage (no
filtering, just a plain decimation) would allow the sample rate pushed
across the USB to be decreased while discarding the unused bandwidth. I
am going to pursue this myself and wondered if I should post any Verilog
changes I make.
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Bringing It Back
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Gregory W Heckler wrote:
Would anyone be interested in an additional decimation stage after the
CIC and the halfband filters? The usable bandwidth is ~25-50% of the
actual post decimation sample rate, an additional decimation stage (no
filtering, just a plain decimation) would allow the sample rate pushed
across the USB to be decreased while discarding the unused bandwidth.
I am going to pursue this myself and wondered if I should post any
Verilog changes I make.
Decimation without filtering is usually not useful, since it will cause
aliasing. Also, at the max USRP decimation rate, the sample rate coming
in is 250ks/s, which is slow enough for even the slowest of computers to
keep up in most cases.
In any case, more verilog code is always better, so send along anything
you come up with.
Matt