I have a narrowband FM receiver running (not based on GNU radio) using
the
usrp library and the USRP hardware. I would be helpful if the USRP
firmware
could reduce the sample to 25 ksps from the current 250 ksps at the
maximum
decimation factor. I want to try run ning my FM receiver on a TI OSK
board
so reducing the data rate would be very helpful.
I am pretty sure I can reduce the ADC sample rate by half, would it be
possible to get some additional decimation from teh FPGA image? I am not
much of an FPGA guy unfortunately.
Philip
Philip B. wrote:
I have a narrowband FM receiver running (not based on GNU radio) using
the usrp library and the USRP hardware. I would be helpful if the USRP
firmware could reduce the sample to 25 ksps from the current 250 ksps
at the maximum decimation factor. I want to try run ning my FM
receiver on a TI OSK board so reducing the data rate would be very
helpful.
I am pretty sure I can reduce the ADC sample rate by half, would it be
possible to get some additional decimation from teh FPGA image? I am
not much of an FPGA guy unfortunately.
You can get more decimation in the FPGA in 2 different ways.
First, you could extend the width of the CIC decimator. There is a
parameter in the beginning of the file called “log2 of max decimation”
or something like that. You’ll also need to fix the shift register at
the end of the file. The limitation here is that going to very high
decimation ratios results in very wide adders, and past a certain width,
they won’t be fast enough for 64 MHz.
The second option is to cascade a second CIC decimator after the first.
This avoids the problem of adder width, but will take more total area.
Matt