AD9862 Functionality

I am trying to figure out how the AD9862 MxFE is setup and I had a few
questions for anyone who may be able to answer them.

RX

  1. Is the internal DLL used to sample faster than 64MSPS? If so,
    what is the DLL rate? Is it possible this would ever want to be used?
  2. Is the Hilbert Filter ever used?

TX

  1. Is the Hilbert Filter ever used?
  2. Is the NCO ever used?
  3. Is the interpolation filter ever used?
  4. Is the fixed [Fs/4,Fs/8] selectable mixer ever used?
  5. Is the TX data ever sent as real-only instead of I/Q from the
    FPGA when it is actually a complex signal?

Aux

  1. Are any of the auxiliary ADC/DACs used for AGC/VCO setting?

Thanks,
Brian

On Mon, Feb 19, 2007 at 10:11:38AM -0500, Brian P. wrote:

  1. Is the NCO ever used?
  2. Is the interpolation filter ever used?
  3. Is the fixed [Fs/4,Fs/8] selectable mixer ever used?
  4. Is the TX data ever sent as real-only instead of I/Q from the
    FPGA when it is actually a complex signal?

Aux

  1. Are any of the auxiliary ADC/DACs used for AGC/VCO setting?

Thanks,
Brian

Hi Brian,

RX

  1. Is the internal DLL used to sample faster than 64MSPS? If so,
    what is the DLL rate? Is it possible this would ever want to be used?

No. IIRC the A/D won’t run faster than 64MS/s.

  1. Is the Hilbert Filter ever used?

No.

TX

  1. Is the Hilbert Filter ever used?

No.

  1. Is the NCO ever used?

Yes, all the time (both coarse and fine)

  1. Is the interpolation filter ever used?

Yes, always.

  1. Is the fixed [Fs/4,Fs/8] selectable mixer ever used?

Yes.

  1. Is the TX data ever sent as real-only instead of I/Q from the
    FPGA when it is actually a complex signal?

No, we always send I/Q to the 9862. There are a couple of use cases
where you might want to send real data, but we don’t implement them.

Aux

  1. Are any of the auxiliary ADC/DACs used for AGC/VCO setting?

Yes, all of them. Details depend on the specific daughterboard.
The PLLs are controlled over SPI or I2C.

The code that sets up the AD9862’s is contained in usrp_basic.cc and
usrp_standard.cc. Most of it is in the constructors.

You may also want to take a look at the USRP motherboard schematic to
see how everything is wired together. The aux DAC/ADC’s are all run
to the daughterboards.

Eric

Eric B. wrote:

RX

  1. Is the internal DLL used to sample faster than 64MSPS? If so,
    what is the DLL rate? Is it possible this would ever want to be used?

No. IIRC the A/D won’t run faster than 64MS/s.

The DLL is used to double the sample rate so that the DACs can sample
at 128 MHz. The ADCs stay at 64.

Matt

On Tue, Feb 20, 2007 at 03:50:21PM -0500, Brian P. wrote:

So to just figure out the different decimations/interpolation rates we have:

ADC samples at 64MHz, and passes through both I and Q channels over
the 24-bit RX bus. Internal to the FPGA, the CIC automatically
decimates by a value of at least 4. The halfband decimating FIR
internal to the FPGA decimates by a fixed value of 2.

Yes. Note that some FPGA builds don’t contain the half-band.

This gives a minimum decimation rate of 8, leaving 8Msps going over
the USB of the USRP. Is this correct?

Yes.
With 16-bit I & Q decim = 8 -> 8MS/sec -> 32MB/sec.
With 8-bit I & Q decim = 4 -> 16MS/sec -> 32MB/sec

The data being clocked out of the USRP is at 64Msps.

More precisely, there are two interleaved channels, each running at
32MS/s. The AD9862 interpolates each stream by 4, giving two streams
at 128MS/s.

There are two points that interpolation can happen - inside the
AD9862 and internal to the FPGA. Within the FPGA, the CIC filter is
the interpolating structure and has a variable rate, whereas the
AD9862 has a fixed interpolation rate of 2x if a real-only signal is
being used, or 4x is possible if interleaved with I/Q at 64Msps -
giving the sample rate of I/Q 32Msps.

Is that correct so far?

Yes.

I am unsure what the minimum interpolating rate of the CIC is, or the
maximum for that matter. Can anyone answer?

It’s probably 1 or 2, though I doubt it’s been tested. The (workable)
maximum is determined by the width of the intermediate stages of the
CIC. I believe we’re good to 128 in the FPGA CIC. Matt would know
for sure.

Who sets the interpolation rate of the CIC internal to the FPGA to get
from the specified number of samples per symbol from a modulator block
in GNU Radio to a number that the CIC can interpolate into 64Msps?

The code in usrp_standard.cc controls the FPGA interpolation rate.
The rates do not have to be powers of two. From the user point of
view the net interpolation rate must be in [4, 512] and a multiple of 4.

This is all controlled in usrp_standard.cc. I suggest that you take a
look at it :wink:

Or is a modulator block required to do things in powers of 2 when
connected to a USRP?

No. You might want to start looking at for example, the gmsk
modulator/demod: gnuradio-core/src/python/gnuradio/blksimpl/gmsk.py

Thanks,
Brian

Eric

So to just figure out the different decimations/interpolation rates we
have:

ADC samples at 64MHz, and passes through both I and Q channels over
the 24-bit RX bus. Internal to the FPGA, the CIC automatically
decimates by a value of at least 4. The halfband decimating FIR
internal to the FPGA decimates by a fixed value of 2.

This gives a minimum decimation rate of 8, leaving 8Msps going over
the USB of the USRP. Is this correct?

The data being clocked out of the USRP is at 64Msps. There are two
points that interpolation can happen - inside the AD9862 and internal
to the FPGA. Within the FPGA, the CIC filter is the interpolating
structure and has a variable rate, whereas the AD9862 has a fixed
interpolation rate of 2x if a real-only signal is being used, or 4x is
possible if interleaved with I/Q at 64Msps - giving the sample rate of
I/Q 32Msps.

Is that correct so far?

I am unsure what the minimum interpolating rate of the CIC is, or the
maximum for that matter. Can anyone answer?

Who sets the interpolation rate of the CIC internal to the FPGA to get
from the specified number of samples per symbol from a modulator block
in GNU Radio to a number that the CIC can interpolate into 64Msps? Or
is a modulator block required to do things in powers of 2 when
connected to a USRP?

Thanks,
Brian

Eric,

Thanks for all the answers so far. I am really getting a grasp of
everything going on within the USRP. I really appreciate it.

On 2/20/07, Eric B. [email protected] wrote:

The code in usrp_standard.cc controls the FPGA interpolation rate.
The rates do not have to be powers of two. From the user point of
view the net interpolation rate must be in [4, 512] and a multiple of 4.

This is all controlled in usrp_standard.cc. I suggest that you take a
look at it :wink:

I have been perusing it, and I will definitely take a closer look.
Thanks!!

Or is a modulator block required to do things in powers of 2 when
connected to a USRP?

No. You might want to start looking at for example, the gmsk
modulator/demod: gnuradio-core/src/python/gnuradio/blksimpl/gmsk.py

I suppose I should clarify the rates. All bandwidths have to be some
decimation from 64Msps that is also divisible by 4. For example, I
could not choose to run a bandwidth of 1.2MHz through the USRP.

Is there an inherent sample frequency of 8Msps when dealing with the
USRP? It seems with 16-bit complex data, the USB is able to transfer
8Msps. If I set the GMSK modulator to have 20 samples per symbol,
will that give me an effective bandwidth of 400kHz?

Thanks,
Brian

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