AD9862 ADC halfband

From the AD9862 data sheet:

“For signals with maximum frequencies less than or equal to 3/16 the ADC
sampling rate, fADC, the decimate by 2 filter (or half-band filter) can
be used to provide on-chip suppression of out-of- band images and noise.
When data is present in frequencies greater than 1/4 fADC, the decimate
by 2 filter can be disabled by switching the filter out of the circuit.
The decimation filter allows the ADC to oversample the input while
decreasing the output data rate by half. The two main benefits are a
simplification of the input antialiasing filter and a slower data
interface rate with the external digital ASIC. The decimation filter is
an 11 tap filter and suppresses out of band noise by 38 dB…”

Is this halfband bypassed by default? Is this configurable from Python?

Thanks,

  • Lee

Lee P. wrote:

interface rate with the external digital ASIC. The decimation filter is
an 11 tap filter and suppresses out of band noise by 38 dB…"

Is this halfband bypassed by default? Is this configurable from Python?

The RX halfbands are bypassed. There is no real need to used them
because we do decimation and filtering in the FPGA. Using them narrows
the IF range you can use.

Matt