About Latency

Hi all:

I have two questions about Gnuradio latency:

  1. In transmit path, the USB delay is constant due to the 32KB buffer
    between “signal source output” and “USB”. If the sampling rate is 1MS/s
    and
    each sample is complex 16 bits( sample size=4bytes), we can get the USB
    latency = 8ms. But how do we estimate the delay of signal processing by
    processor and USRP? I think these delays are variable depending on how
    complex the signal is and how fast the processor is. But are there any
    ways
    to determine what is the range of these delays?

  2. fusb_options define two parameters of “fusb_nblocks” and
    “fusb_block_size”.
    This function should be used to decrease the delay of USB. But, if we
    choose
    any value of number of blocks and block size, say, nblock=8 and
    block_size
    =2048, does that mean we need to have larger time to pass through the
    8*2048
    Bytes packet than the smallest allowed 512 Bytes? So, in this logic, the
    latency of usb will increase although the throughput is increased. Am I
    correct? If not, what’s wrong with my thought?

Thanks for ur reply advance!!

KC Huang

KC Huang-

I have two questions about Gnuradio latency:

  1. In transmit path, the USB delay is constant due to the 32KB buffer
    between “signal source output” and “USB”. If the sampling rate is 1MS/s and
    each sample is complex 16 bits( sample size=4bytes), we can get the USB
    latency = 8ms. But how do we estimate the delay of signal processing by
    processor and USRP? I think these delays are variable depending on how
    complex the signal is and how fast the processor is. But are there any ways
    to determine what is the range of these delays?

Compared to PC data transfer, FPGA logic delays should be negligible.
For example,
FIR filtering in FPGA logic contributes at least one clock cycle per
sample to
latency (64 MHz clock). It could be more than one clock per, but I
don’t know the
FPGA code and the Cyclone (which is an old FPGA) well enough to say
whether Matt was
able to implement single-cycle MAC. To get some idea of comparison,
depending on how
it’s implemented, a 16-tap FIR filter might add from 250 nsec to a few
usec.

-Jeff

On Thu, Oct 04, 2007 at 03:22:40PM -0400, KC Huang wrote:

Hi all:

I have two questions about Gnuradio latency:

  1. In transmit path, the USB delay is constant due to the 32KB buffer
    between “signal source output” and “USB”.

You misunderstand how things work.

Please take a look at Thomas S.'s paper
http://nesl.ee.ucla.edu/document/show/242
and then if you’ve still got questions, please post again.

Eric

On Thu, Oct 04, 2007 at 09:46:36PM +0800, KC Huang wrote:

So, does that mean if u have large product of fusb_block_size and
fusb_nblock, then the theometical maximum delay will be increased?
Therefore, I think that the range of USB latency is also increased. Please
correct me if I am wrong. Thanks!

KC

Yes that is true.

If you’re trying to minimize latency you want the smallest values that
work reliably (no over/underruns) and with acceptable overhead. If
you enable real time scheduling, you can reliably use smaller values.

Try fusb_block_size 2048 and fusb_nblock 4 or 8. You may be able to
run with fusb_block_size 1024. It depends on your data rate across
the USB.

Eric

Hi,

Where did he get this equation from? (What is this equation f?)

Hi Eric:

I have already read that paper before. As that paper mentions, the USB
delay
is according to the equation

f(512, fusb_block_size*fusb_nblock)

fs*sample_size ,
which
f(x,y) is at least x and at most y

Hi Eric:

I have already read that paper before. As that paper mentions, the USB
delay
is according to the equation

f(512, fusb_block_size*fusb_nblock)

fs*sample_size ,
which
f(x,y) is at least x and at most y

So, does that mean if u have large product of fusb_block_size and
fusb_nblock, then the theometical maximum delay will be increased?
Therefore, I think that the range of USB latency is also increased.
Please
correct me if I am wrong. Thanks!

KC

----- Original Message -----
From: “Eric B.” [email protected]
To: “KC Huang” [email protected]
Cc: [email protected]
Sent: Friday, October 05, 2007 8:29 AM
Subject: Re: About Latency

oooo never mind just realized

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