I am working on estimating the delay between a Tx and an Rx using a
stream
of packets modulated in a BPSK scheme (1 Mb/s) with a pair of N210.
(Sampling of 8 Mbits/s)
I want to know if the latency added by the portion(*) of [ FPGA - DAC -
RF
front end to the antenna *2 (Rx Part) ] could be determined for a giving
set
of parameters (transmission-reception)
I am interested in estimating the range of this latency (tens? hundreds
of
microseconds?)
Then, could this latency be considered as insignifiant versus the
latency of
the local network and the latency of Ethernet queue processing
(Encapsulation/Decapsulation). (for eg. both Rx and tx ethernet latency
are
fluctuating between 1 to 1.5 msec.)
Another point, how is the latency of the portion (*) varying.
All explanation are appreciated, thank you in advance.
I think I’m having trouble understanding your question. I’m not sure
what
you want to measure, or how you intend to measure it.
For starters, there isn’t really a shared concept of ‘time’ between the
FPGA and the analog components. The FPGA operates in terms of clocks…
which don’t exist on the analog front-end. I suppose you could try to
measure it in real-world ‘time’, but figuring out how to do that would
be
incredibly hard, and then the instrumentation you would need to do it
would
be even harder (probably?).
Are you asking about measuring the group delay of the analog components?
If
that’s the case, the throwing everything into a simulator is your best
bet.
Anyway, sorry for the confused response. I don’t think I’m understanding
your question correctly.
Hint 1: If both 210s are on the same PPS and frequency reference and
the FPGA clocks are synchronized to the PPS, you can schedule the
transmit and receive to within one tick of the 100 MHz ADC clock.
Hint 2: Cross correlate the transmitted and received samples. The lag
will be independent of Ethernet and IP delays.
I’ve been doing some theoretical calculations on the group delay
estimation
and found that this part is giving negligible latency compared to the
Ethernet portion between USRP and host.
Ok I will try using a common clock ref and input PPS
Scheduling the transmit and receive to within one tick of the 100 MHz
ADC clock: Can that be done into the host GNU radio code or am supposed
to
move the code to the FPGA.
Is that the samples count method to get accurate time-stamping ?
Can you please explain to me more about the concept of cross
correlating transmitted
and received samples.