Can someone with Verilog experience please help me with a question or
two? I have done some VHDL before, so I am not entirely clueless.
Is it possible to bit selects with an array of registers? How do I
select the upper eight bits from ram_array if I have the following?
reg [15:0] ram_array [0:15];
The difference between
val <= #1 input[15:12]; and
val = input[15:12];
when it is inside an always @(posedge clk) block is that the = sign
operation is sequential, right and that <= operations are in parallel?
The #1 means a delay of 1, right? So if I for instance have data
going through a filter with the following code
always @(posedge clk)
tap1 <= #1 input;
tap2 <= #1 tap1;
tap3 <= #1 tap2;
the #1 ensures that tap1 gets updated before tap2?
And the last question is regarding the assign statement. I know that
when we have commands inside a always @(posedge clk) block, we look at
clock changes and do certain things. Do we use the assign statement
if we for instance want to change an output when in input changes or
if we have an output that is not dependent on a clock? I still don’t
exactly know when to use an assign instead if putting it inside an
always block? What’s the rule of thumb?
Thanks in advance.
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