A Verilog question or two


#1

Hi

Can someone with Verilog experience please help me with a question or
two? I have done some VHDL before, so I am not entirely clueless.

Is it possible to bit selects with an array of registers? How do I
select the upper eight bits from ram_array[2] if I have the following?

reg [15:0] ram_array [0:15];

The difference between

val <= #1 input[15:12]; and
val = input[15:12];

when it is inside an always @(posedge clk) block is that the = sign
operation is sequential, right and that <= operations are in parallel?
The #1 means a delay of 1, right? So if I for instance have data
going through a filter with the following code

always @(posedge clk)
begin
tap1 <= #1 input;
tap2 <= #1 tap1;
tap3 <= #1 tap2;
end

the #1 ensures that tap1 gets updated before tap2?

And the last question is regarding the assign statement. I know that
when we have commands inside a always @(posedge clk) block, we look at
clock changes and do certain things. Do we use the assign statement
if we for instance want to change an output when in input changes or
if we have an output that is not dependent on a clock? I still don’t
exactly know when to use an assign instead if putting it inside an
always block? What’s the rule of thumb?

Thanks in advance.

Sebastiaan


Sebastiaan H.
Radar and Remote Sensing Group, University of Cape Town
Tel: +27 83 305 5667


#2

On Tue, Oct 14, 2008 at 10:45 AM, Sebastiaan H. removed_email_address@domain.invalid
wrote:

Hi

Can someone with Verilog experience please help me with a question or
two? I have done some VHDL before, so I am not entirely clueless.

Is it possible to bit selects with an array of registers? How do I
select the upper eight bits from ram_array[2] if I have the following?

reg [15:0] ram_array [0:15];

Using my Google prowess:

http://www.geda.seul.org/mailinglist/geda-dev33/msg00056.html

always @(posedge clk)
clock changes and do certain things. Do we use the assign statement
if we for instance want to change an output when in input changes or
if we have an output that is not dependent on a clock? I still don’t
exactly know when to use an assign instead if putting it inside an
always block? What’s the rule of thumb?

Here area couple good pages to read about all that:

http://www.asic-world.com/verilog/verilog_one_day3.html
http://www.asic-world.com/verilog/timing_ctrl1.html

Thanks in advance.

You’re welcome.

Brian


#3

On Wednesday 15 October 2008 01:15:48 Sebastiaan H. wrote:

always @(posedge clk)
begin
tap1 <= #1 input;
tap2 <= #1 tap1;
tap3 <= #1 tap2;
end

the #1 ensures that tap1 gets updated before tap2?

According to what I have read with about synthesis tools the delays will
be
ignored totally.

I see a lot of it though, so I don’t know if it’s superstition or the
manual
lies.

The above code will do those 3 assignments simultaneously.

I found the following to be very very useful in explaining things in
detail
without getting bogged down in the useless level of crud you find in a
lot of
text books (eg how CMOS gates are made…)
http://web.mit.edu/6.111/www/f2005/

And the last question is regarding the assign statement. I know that
when we have commands inside a always @(posedge clk) block, we look at
clock changes and do certain things. Do we use the assign statement
if we for instance want to change an output when in input changes or
if we have an output that is not dependent on a clock? I still don’t
exactly know when to use an assign instead if putting it inside an
always block? What’s the rule of thumb?

always @(posedge clk) will only cause things to change on the positive
edge of
clk (like it says :slight_smile: - using assign will cause things to change at any
time.
(sequential vs combinational). You can also do combinational logic
inside an
always block (see page 5 onwards of L04 above).

PS I am far from a Verilog guru so if there is one reading please
correct any
mistakes I have made :slight_smile:


#4

2008/10/14 Daniel O’Connor removed_email_address@domain.invalid:

According to what I have read with about synthesis tools the delays will be
ignored totally.

I see a lot of it though, so I don’t know if it’s superstition or the manual
lies.

I think the delays are just for simulation. In synthesis the
assignments take a real amount of time to complete (because it’s
hardware). If you are dependent on that delay, you need to signify
that in simulation, otherwise the assignment would occur at the same
simulation timestep as everything else and you could be using new data
instead of old. Most likely synthesis ignores them, but they are
needed for the simulation (I’m not 100% sure, I usually remove all
such delays before synthesis testing).

Jason


#5

On Thursday 16 October 2008 01:00:19 Jason U. wrote:

simulation timestep as everything else and you could be using new data
instead of old. Most likely synthesis ignores them, but they are
needed for the simulation (I’m not 100% sure, I usually remove all
such delays before synthesis testing).

Hmm… I think it’s more likely to be superstition for broken simulators
then…

A book I have (Kilts - Advanced FPGA design) states that
“Delays are always ignored by synthesis tools, and this type of modeling
can
easily create mismatches between simulation and synthesis.” (page 167).