InBand Signaling: Schedule

GNU Radio
1

Hello,

We (George and me) have added a schedule page to the wiki :
http://gnuradio.org/trac/wiki/InBandSignalingSched

Could you please look it over, add anything missing and suggest
deadline. I can work on the FPGA, but I don’t think I will be very
efficient. It would be great if you could suggest an entry point for
both of us.

Thanks,
George and Thibaud

2

On 3/1/07, Thibaud H. [email protected] wrote:

Hello,

We (George and me) have added a schedule page to the wiki :
http://gnuradio.org/trac/wiki/InBandSignalingSched

Could you please look it over, add anything missing and suggest
deadline. I can work on the FPGA, but I don’t think I will be very
efficient. It would be great if you could suggest an entry point for
both of us.

The diagram should have the FPGA talking to both the AD9862 and the
daughterboard. You can think of them on the same level since no real
communication is done digitally with the AD9862 - only the analog
signal really follows the chain as it is currently drawn.

As for entry points, I think writing small I2C and SPI modules that
can read and write the bus is a good start. That should get you
familiar enough with an interface.

A top level design might be a good idea to look over and do a design
review. Maybe map out what module names and interfaces are going to
connect to where. Go over the use cases for how the packets are going
to be sent, processed, etc.

There is still a lot of planning to do before you shoudl really go
ahead and attack this problem. You don’t want your Verilog to become
spaghetti because it will just make it BIG. Draw out your FSMs. I
personally can’t stand bubble charts and prefer ASM charts - but
either way, these sort of things should be planned out.

Here is a link on ASM charting:
http://uhaweb.hartford.edu/jmhill/suppnotes/AsmChart/index.htm

I am sure there are others out there.

Moreover, unit testing your modules is a very good idea. Get in the
habit of writing testbenches - they will always come in handy.

This should be plenty to keep you guys busy while Eric finishes
writing up the m-block stuff. Go with his interface that he specified
and figure out what things have to happen to tune the daugherboards,
set the AD9862, etc. Try to get down into the control of the entire
USRP. What does the FX2 do? What operations would have to happen in
a TDMA + FDMA sequence to make sure everything works properly? What
does the tune() method do in Python for the daughterboards?

Good luck.

Thanks,
George and Thibaud

Brian