(1) From examining the code, I find that I can read the rssi/clipping indicator register associated with ADC n with usrp._u._read_fpga_reg( n+5 ) where usrp is an instance of usrp.source_s. Question: Is there a better/preferred/higher-level function to access the rssi/clipping register? (2) When I use the above to poll the rssi/clipping register while using usrp.source I get glitches (at the rate of several per minute) in the usrp data stream. A modified version of test_counting.py (attached) shows several types of errors. In order of decreasing frequecy, they are: (a) single-bit errors; (b) multiple-bit errors within each 16-bit value (but never multiple bit errors spanning consecutive 16-bit values); (c) two count values missing; (d) one count value missing; (e) random value inserted in count sequence; and (f) multiple instances of 0 or 0xffff inserted in the sequence. Eventually (usually within an hour) the program will terminate with "usb_reap_async: timeout error". This happens on Windows XP/SP2 with either MSYS/MinGW or Cygwin. Hardware is AMD Sempron 3100+. GNU Radio is latest svn version. Request: Would a few people be willing to try this short test program to see what it does on their system? (It should produce a few lines of "gr_check_counting" messages as it starts then produce nothing else until you kill it.) This appears to be a USB problem, except that none of the usrp requests usrp._u.set_pga( which, 0. ) usrp._u.read_aux_adc( 0, 0 ) usrp._u.noverruns() cause problems, while the request usrp._u._read_fpga_reg( 4 ) seems to produce "usb_reap_async: timeout error" the first time it is issued if the flow graph is running (but executes ok before the flow graph is started). Questions: Should we expect usrp register read requests to interfere with data transfers? Is there a better way to access the rssi/clipping indicator? Will mblocks allow internal USRP information (such as the rssi registers) to be included in data packets read from the USRP? Thanks for any help (and thanks, Eric, for pointing to test_counting.py). -- Don W.
on 2007-01-06 19:30
on 2007-01-19 16:30
On Thu, Jan 04, 2007 at 04:31:39PM -0500, Don Ward wrote: > > Questions: Should we expect usrp register read requests to interfere with > data transfers? Is there a better way to access the rssi/clipping > indicator? Will mblocks allow internal USRP information (such as the rssi > registers) to be included in data packets read from the USRP? Until we switch to "in-band signaling", register read/writes are handled using USB command packets which have higher priority than bulk transfers. They are are also implemented in the FX2 via relatively slow bit-banging code. While it's bit-banging, it's not forwarding packets between the GPIF and the USB bus. Given the small amount of FIFO implemented in the FPGA, under/overruns are possible. Eric