hello!
sorry if it has reached previously…
in one of the previous conversation you guys discussed about modifying
the
FPGA code to shut off the TX once the packet is sent…
i tried an attempt on it.
In the tx_buffer.v file i set all output to be zero either at reset or
tx_empty i.e. the rd_empty from fifo_4k.
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset | tx_empty) // ----------------> if tx_empty then too
output
be zero
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128’h0;
load_next <= #1 4’d0;
end
else
if((load_next != channels) & !tx_empty)
begin
load_next <= #1 load_next + 4’d1;
case(load_next)
4’d0 : tx_i_0 <= #1 fifodata;
4’d1 : tx_q_0 <=…
…
…
…
Now with this FPGA design i tried fsk_tx.py and fsk_rx.py…
the problem is, when i try transmission in repeat mode only then i see
the
channel becoming free once i close the transmission…
but if i try just one time transmission, the carrier is still present
after
the transmission ends…
any idea why this is happening?
thanks,
amit…
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What daugherboard(s) are you using?
What you’re describing is currently tough with the basic tx since it’s
effectively “always on” once you fire it up. If you underrun, the
FPGA will continue transmitting the same value to the DAC (which has
the upconverter in it), thus even if you’re “not transmitting”, it’s
highly likely that you really are still transmitting.
There are a couple of ways to solve/work-around this behavior:
- use a RFX- board with auto transmit switching enabled.
- modify the FPGA code such that when the TX fifo is empty, you
ramp the value fed to the DAC down to zero over say 8 clocks.
If this doesn’t make sense to you, please attach an oscilloscope to
the DAC output and watch what you’re currently getting.