Forum: GNU Radio FR_RX_MUX in fpga_regs_standard.v

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2bba490f3cdba9178645e1ff4652ba8d?d=identicon&s=25 amit malani (Guest)
on 2006-04-25 00:17
(Received via mailing list)
Hi!
i cant figure out how exactly this register works.


// See below for DDC Starting Phase

//
------------------------------------------------------------------------
//  configure FPGA Rx mux
//
//    3                   2                   1
//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
// +-----------------------+-------+-------+-------+-------+-+-----+
// |      must be zero     | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
// +-----------------------+-------+-------+-------+-------+-+-----+
//
// There are a maximum of 4 digital downconverters in the the FPGA.
// Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I &
Q.
//
// DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
//
//   0 = DDC input is from ADC 0
//   1 = DDC input is from ADC 1
//   2 = DDC input is from ADC 2
//   3 = DDC input is from ADC 3
//
// If Z == 1, all DDC Q inputs are set to zero
// If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2,
Q1 & Q0
//
// NCH specifies the number of complex channels that are sent across
// the USB.  The legal values are 1, 2 or 4, corresponding to 2, 4 or
// 8 16-bit values.

`define FR_RX_MUX                 7'd38

//
------------------------------------------------------------------------

what values for the two bits of each of the Q specify?....

can you please explain with an example how exactly both I and Q
outputs are used?
How is it in case of FM receptions?

not on the same line.......
but how exactly USB receives the the stream?

Is the data pulled from host by constantly polling USRP and check for
data or does the USRP raises an interrrupt when the data is available?

I want to know this to implement carrier sensing in FPGA and want to
convey the state to host asynchronously.
is that possible or does the Host will need keep on polling or keep on
reading the readable Registers on FPGA(i thought of using those
readable regs as shared memory between host and FPGA)

i hope i am clear about my queries...

thanks,
amit
745d8202ef5a58c1058d0e5395a78f9c?d=identicon&s=25 Eric Blossom (Guest)
on 2006-04-25 00:36
(Received via mailing list)
On Mon, Apr 24, 2006 at 06:14:17PM -0400, amit malani wrote:
> Hi!
>
> i cant figure out how exactly this register works.

Amit,

I strongly suggest you do the work to acquire a basic grip on how GNU
Radio and the USRP work in their normal configuration before you
attempt to hack the FPGA code.  Dawei Shen has put together a nice set
of tutorials that will get you started: http://www.nd.edu/~dshen/GNU

If I & Q processing is not clear to you, please see any of a number of
DSP and digital communications text books.  Several are listed at
http://comsec.com/wiki?SuggestedReading

With regard to data transfer across the USB, once you've opened the
USRP and enabled it, the data streams across the USB.  This is all
handled for you by the standard software.  No user visible interrupts
are involved.

If you want to develop an understanding for how to talk to the USRP
without using GNU Radio, start with usrp_standard.h and usrp_basic.h
in usrp/host/lib.  That's the high level C++ interface that GNU Radio
uses.

Eric
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