Hmm, I don't think so: What I apply to board A ADC0 shows up on scope0, and what I apply to board A ADC1 shows up on scope1, so there are definitely two different ADCs involved. Looking at the scope traces they are connected as set by the line self.uhd_usrp_source_0.set_subdev_spec("A:A A:B", 0) i.e: DDC-channel0, input I from board A, ADC0 DDC-channel0, input I from board A, ADC1 Both Q-inputs to GND It appears, that the gain settings are somehow skewed up. I am sure that the gain for both ADCs attached to same LFRX-board got be set individually. Do I need a special FPGA code? Wolfgang >Those are two DDC channels, derived from the same physical, analog, hardware and ADC. > > >The LFRX itself has no gain-setting device, but the ADC does, so when you set the gain on the ADC, you're setting the gain for both DDC-derived channels.
on 2013-05-30 06:55
on 2013-05-30 07:34
On 05/29/2013 11:53 PM, Wolfgang Buesser wrote: > > Both Q-inputs to GND > > It appears, that the gain settings are somehow skewed up. > I am sure that the gain for both ADCs attached to same LFRX-board got be set individually. > Do I need a special FPGA code? > > The good news is that there is already software control for this. The bad news is, there isnt an API to expose this edge case of ADC as two unrelated streams with individual gain. See: https://github.com/EttusResearch/uhd/blob/master/h... -josh