Forum: GNU Radio Input Clock For FPGA

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A8dda2c33e6ce6210f710e80bf15bd02?d=identicon&s=25 Fahimeh Rezaei (Guest)
on 2009-06-01 03:19
(Received via mailing list)
Hi Dear all Friends
I have some questions regardin schematic of GNU Radio
1- what is exact voltage of DVDD_CLK:1 and VREF_CLK:1 and othe such
lables I
could not find that?
2- since master clock is comming from OUT0 of AD9513 what is the input
frequency for CLK pin of AD9513? since I guess that OUT0 is devided by 6
based on S0-S10 pin status, however I can not get the exact input value
for
CLK (pin2) of AD9513!
can anybody help me as soon as possible?
thanks
regards
3596cfe1d579c65b9babd35e8787977c?d=identicon&s=25 Matt Ettus (Guest)
on 2009-06-01 21:37
(Received via mailing list)
Fahimeh Rezaei wrote:
> Hi Dear all Friends
> I have some questions regardin schematic of GNU Radio
> 1- what is exact voltage of DVDD_CLK:1 and VREF_CLK:1 and othe such
> lables I could not find that?

DVDD_CLK is 3.3V.  VREF_CLK is generated by the clock chip, and its
exact voltage doesn't matter.  It is somewhere around 2.2V.

> 2- since master clock is comming from OUT0 of AD9513 what is the input
> frequency for CLK pin of AD9513? since I guess that OUT0 is devided by 6
> based on S0-S10 pin status, however I can not get the exact input value
> for CLK (pin2) of AD9513!
> can anybody help me as soon as possible?

Both the input and output clocks are all 64 MHz.

Matt
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