Hi all
I’m doing the project on USRP, a digital data transmission system. I use
RFX2400 daughterboard. I want to implement something like 802.11b/g
system, but I would like to put all the modulation/demodulation work,
error detection/correction and MAC protocol on FPGA, in order to make
the system independent from PC. I will feed a data stream to the USRP
and want to use the fastest rate possible, and I want the receiver to
send only some sort of acknowledgement for the received packets
(cumulative acks may be considered). The first question is, is it
possible to fit such a program on USRP’s Cyclone? As I understand,
existing code takes almost all the space on FPGA, but it’s possible to
remove unused parts (for ex., I don’t need all the channels) and free
some space. Another question is which modulation technique will take
least space while doing the job (i need at least 25 meters range)? And I
also wonder if the multipath propagation will be a big problem? If yes,
is there an easy way to deal with it?
Any help will be appreciated! Thanx in advance for your answer
Andrey Brandis
On Tue, Mar 3, 2009 at 6:51 AM, Andriy B. [email protected]
wrote:
FPGA, but it’s possible to remove unused parts (for ex., I don’t need all
the channels) and free some space. Another question is which modulation
technique will take least space while doing the job (i need at least 25
meters range)? And I also wonder if the multipath propagation will be a big
problem? If yes, is there an easy way to deal with it?
Any help will be appreciated! Thanx in advance for your answer
It could fit into the Cyclone. It really all depends on the bandwidth
you want to use, and how efficient of an FPGA coder you are. What you
are proposing requires pretty considerable skill not only in
reprogramming the FPGA but also in wireless communications.
Modulation, symbol rate, FEC scheme, distance, line-of-sight, transmit
power - the list goes on for quite a while. These are the parameters
you have to tweak to get your design to fit within the FPGA.
As for multipath, you can try to use a RAKE receiver to help mitigate
this as I don’t think the Cyclone could really handle having an
equalizer run at anything other than extremely low rates.
Good luck!
Brian
Brian P. wrote:
this as I don’t think the Cyclone could really handle having an
equalizer run at anything other than extremely low rates.
You may also want to start with some of the SPAN 802.11 code which
detects the beginning of 802.11 packets and does the despreading in the
FPGA:
https://www.cgran.org/wiki/SPAN80211b
https://www.cgran.org/browser/projects/span_80211b/trunk/src/fpga