Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI and a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through Ruby. It lets you create complex Verilog test benches easily and wholly in Ruby. â€¢ See http://ruby-vpi.rubyforge.org for details. â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â” Version 17.0.0 (2007-07-22) This release makes the Ruby-VPI testing framework more lightweight by reducing the number of files and parameters involved. Caution â€¢ The generate_test.rb and convert.rb executables have been replaced by a single ruby-vpi executable to avoid name conflicts with other software. They are now accessed using the ruby-vpi generate and ruby-vpi convert commands respectively. â€¢ The --name parameter has been removed from the automated test generator. Similarly, you can no longer insert an arbitrary name in a testâ€™s file names (see the user manual for details). â€¢ The DEBUG environment variable, which controls wether the test runner starts the interactive debugger, has been renamed to DEBUGGER. â€¢ The SIMULATOR_TARGET and SIMULATOR_INCLUDES parameters have been eliminated from test runners. The former is detected automatically. As for the latter, you can specify paths to directories in the SIMULATOR_SOURCES parameter instead. â€¢ The bench.rb and bench.v files of a generated test are (1) no longer generated by the test generator and (2) are now ignored. You must move the functionality provided by these files into design.rb and your Verilog moduleâ€™s source file respectively. â€¢ The design.rb and proto.rb files are now loaded into a separate namespace (Ruby module). For example, if the Verilog module under test has the name â€œcounterâ€ and the design.rb file defines a class named â€œFooâ€, then that class will be accessible as â€œCounter::Fooâ€. â€¢ The global Vpi::simulate method has been replaced by the cycle! method in the design.rb file. â€¢ The simulate! method in the proto.rb file has been renamed to feign! for accuracy. â€¢ The RubyVpi module has been renamed to RubyVPI. â€¢ RSpec >= 1.0.0 is now required by Ruby-VPI. â€¢ The project license has been further simplified. Repairs â€¢ Restored support for Enumerable methods in Vpi::Handle. â€¢ The specification now begins to execute at simulation time 0. Previously it began at simulation time 1. Improvements â€¢ The bench.rb and bench.v files of a generated test have been eliminated! One important benefit is that the Ruby interface to the Verilog module under test is now a direct reference, whereas previously it was an indirect reference (it pointed to the Verilog module defined in bench.v, which in turn wrapped around the actual Verilog module under test). As a result, you can now access the internals of the Verilog module under test by simply calling methods on the Ruby interface, as you would naturally expect to be the case. â€¢ The â€œaâ€ accessor, which returns an array of child handles, has been added to the method naming format for accessing child handles. â€¢ All parameter objects in the Verilog module under test are automatically made available as constants. For example, if the Verilog module under test has the name counter and has a parameter object named WIDTH, then you can access the integer value of that parameter using Counter::WIDTH. â€¢ The automated test generator now tries to automatically detect the clock and reset signal from Verilog module declarations. â€¢ Exceptions are now raised when you try to write to a read-only VPI property, such as VpiName. â€¢ Added high?, high!, low?, and low! methods to the Vpi::Handle class. â€¢ Revised the user manual by removing unnecessary sections and adding newer material from my masterâ€™s thesis. Contributions â€¢ Added Jacinto Shy IIâ€™s register file example to Ruby-VPI. It can be found in samp/register_file/.
on 2007-07-23 00:02