Hi Brian and friends,
Well, yes, CCS is the Code Composer Studio, which I am using to
interface with the TI DSKs…and my project currently involves working
on data which is being fed to/from the FPGA…so I need the FPGA as a
working programmed device.
Yes, I do know how to write testbenches in verilog n all, but as I told
u, I am complete novice to the USRP, which is being used for my current
project.
You told me that the host side handles fft-ifft processing, can you
please enlighten me on that? I mean, how exactly do we feed the raw data
in for the fft processing and the other way…just wanted to know how
these steps are done?
One of my steps in the project is to perform fft on the data to be
transmitted and perform ifft on the data received, so if this step is
clarified, it would really do a big world of good to me. Then,
constructing a fft-ifft processing block and programming the fpga for
that matter can be done away with.
As regards the pin assignment, do you mean that the pin mapping shown
the pin assignment editor is the final pin mapping, or is it changeable
too? Because if its permanent, then I can assume that the onboard clock
is up and running to the fpga whenever i perform my tests on the board.
Thanks a lot for your continued support in this regard.
Regards,
Kuntal
the fpga as a fft-ifft block, which does the fft-ifft as required on being
fed by the data from the DSK. This is what I am aiming at.
Have you written an FFT-IFFT block in Verilog yet? I don’t know what
CCS is - you will have to enlighten me.
You should do all this inside a simulation first before trying to
accomplish it in the actual hardware. Do you know how to write a
testbench in Verilog?
So, after building the radio, i tried running the sample examples as given
and they ran perfectly. So,
Brian, do u now intend to tell me that I should I try Matt’s usrp_std and
program the fpga with that. Even if I do that, how do I assign the pins for
the fpga, I mean, the external IO pins. Or is there any relevant
documentation on this anywhere?
The external IO pins should not have to be mapped if you use Matt’s
Quartus II project. It will already have the pins mapped to where
they have to be mapped.
When you insert your FFT-IFFT, you should just instantiate your module
within the pipeline somewhere. That pipeline is somewhat described
here:
http://gnuradio.org/trac/wiki/UsrpFPGA
As a side note - GNURadio can process FFT and IFFT on the host side as
it is - is there a reason you’re doing the FFT and IFFT within the
FPGA instead?
Thanks a lot for the support.
Regards,
Kuntal
Brian