# \[USRP-users\] Register reading from the USRP2 **URL:** \ **Category:** GNU Radio\ **Created:** [January 19, 2012, 4:38pm UTC](https://www.ruby-forum.com/t/usrp-users-register-reading-from-the-usrp2/215927 "2012-01-19T16:38:28Z")\ **Posts on this page:** 2\ **Page:** 1
**Author:** ![dubstep](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/d/cdc98d/32.png) [@dubstep](https://www.ruby-forum.com/u/dubstep)\ **Post date:** [January 19, 2012, 4:38pm UTC](https://www.ruby-forum.com/t/usrp-users-register-reading-from-the-usrp2/215927/1 "2012-01-19T16:38:28Z")
Hello, I am working with a USRP2 board and the old GNU Radio driver (not the UHD driver) under Ubuntu 10.04. I added a module to the FGPA in the file named u2\_core.v and I defined some setting registers in order to control it. On the other hand, in the host side, I used the poke32 method to set the values of each register. My doubt is whether is possible or not, to read from the host the value of a FPGA register, such as the output of my module. I thouht that the method named peek32 could be useful but it is confusing for me. If I understood right the architecture, the AeMB processor loads from the memory (defined by the memory\_map.h file) the value of every setting register via the Slave #7 (Setting Bus) and by using the poke32 method I tell the AeMB processor (modifying the memory) what value it has to load. Hence, the communication flows from the AeMB processor to the registers. My question is: Is it possible to establish the communication the other way around? I mean, load a setting register value into the AeMB memory so I can read it using the peek32 method. Related to this: - Is there an existing example of the peek32 method usage? Not necessarily of a setting register. From the mailing list I read: “Readback registers are only implemented for states that we need to readback from the device.” Could someone give me an example of this? - The firmware file named memory\_map.h refers to a logic place in the AeMB, right? What FPGA file defines this place? A lot of thanks for any help. Greetings. Eduardo. ---
**Author:** ![eduardoflores](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/e/41988e/32.png) [@eduardoflores](https://www.ruby-forum.com/u/eduardoflores)\ **Post date:** [January 19, 2012, 6:37pm UTC](https://www.ruby-forum.com/t/usrp-users-register-reading-from-the-usrp2/215927/2 "2012-01-19T18:37:18Z")
Eduardo, On Jan 19, 2012, at 7:37 AM, Eduardo Lloret F. wrote: > that the method named peek32 could be useful but it is confusing for > me. > As a back ground there are 2 types of registers in the FPGA memory map, > “Wishbone” and “Setting”. Wishbone is the native bus protocol of the > AeMB and ZPU > processors used in Ettus designs and it’s a relatively simple pipelined > SoC bus. > The USRP2 has only one master on the Wishbone bus, the AeMB/ZPU ad a > bunch of > slave devices. The slaves are hooked upto the master via the module > “wb\_1master”, > and this module defines the memory map of the Wishbone bus. The Settings > bus is > a very simple write only bus, that allows (as you have done) very quick > edits to the code > to add registers. The Settings bus is implemented as a device on the > Wishbone bus > (A bus bridge in ASIC/FPGA design terms), and so a piece of Wishbone > memory map > addresses the setting registers. However as stated it’s a write only > bus, and so to allow > read back from various sources there is another device on the Wishbone > bus called > “wb\_readback\_mux” that allows 32bit data sources to be quickly hooked > up. It has a > different address range than the settings bus as you can see from the > “wb\_1master” > instantiation. Thus you either need to: 1. Hook up the data you want to read to the wb\_readback\_mux and use different addresses to poke32/peek32 to write/read your registers or 2. Create Wishbone protocol registers and add them to the memory map (more work, only worth it if you are adding a major new module) Pay careful attention to which portion of the settings bus you add registers to depending on there clock domain, there is another bus bridge on the settings bus and on one side should be registers on the wb\_clk and on the other side registers driven by dsp\_clk. > memory so I can read it using the peek32 method. > A lot of thanks for any help. > > Greetings. > > Eduardo. > > * * * > > USRP-users mailing list > [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid) > [http://lists.ettus.com/mailman/listinfo/usrp-users\_lists.ettus.com](http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com) p.s Not sure why but your message didn’t appear on the usrp-users mailing list -ian