# USRP.. programming the FPGA **URL:** \ **Category:** GNU Radio\ **Created:** [February 26, 2007, 4:39pm UTC](https://www.ruby-forum.com/t/usrp-programming-the-fpga/86868 "2007-02-26T16:39:03Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![pankaj\_kumar](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/34f0e0/32.png) [@pankaj\_kumar](https://www.ruby-forum.com/u/pankaj_kumar)\ **Post date:** [February 26, 2007, 4:39pm UTC](https://www.ruby-forum.com/t/usrp-programming-the-fpga/86868/1 "2007-02-26T16:39:03Z")
Hello all, I am a student doing a project, which uses USRP board. As a first step of my project i tried to programmin the FPGA, with a verilog code. i am usin QUARTUS 2 for downloding the code, but i am not able to do it. i get a message which says hardware is not found, for information, i am using windows XP and web version of quartus 2 software. i saw the discussion on other topic on this group which looks very in depth technical for me, becoz i dont have so much idea in this, so may be mine discussion will look like a small topic. But anyway, i hope for help and information regarding this. Thank you pankaj ---
**Author:** ![pankaj\_kumar](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/34f0e0/32.png) [@pankaj\_kumar](https://www.ruby-forum.com/u/pankaj_kumar)\ **Post date:** [February 26, 2007, 4:43pm UTC](https://www.ruby-forum.com/t/usrp-programming-the-fpga/86868/2 "2007-02-26T16:43:05Z")
On 2/26/07, pankaj kumar [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid) wrote: > Hello all, > > I am a student doing a project, which uses USRP board. > > As a first step of my project i tried to programmin the FPGA, with a verilog > code. > i am usin QUARTUS 2 for downloding the code, but i am not able to do it. > i get a message which says hardware is not found, How are you connected to the USRP to download the code? I don’t think there are JTAG connections for Quartus II to directly program the FPGA on the board. Instead, the image has to go down over the USB through the USRP libraries supplied with GNU Radio and get programmed by the FX2. Brian ---
**Author:** ![pankaj\_kumar](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/34f0e0/32.png) [@pankaj\_kumar](https://www.ruby-forum.com/u/pankaj_kumar)\ **Post date:** [February 26, 2007, 5:15pm UTC](https://www.ruby-forum.com/t/usrp-programming-the-fpga/86868/3 "2007-02-26T17:15:19Z")
On Mon, Feb 26, 2007 at 07:38:06AM -0800, pankaj kumar wrote: > i saw the discussion on other topic on this group which looks very in depth technical for me, becoz i dont have so much idea in this, so may be mine discussion will look like a small topic. > > But anyway, i hope for help and information regarding this. > > Thank you > pankaj Before trying to modify anything, start by building GNU Radio and running the existing examples. I suggest usrp\_fft.py as a starting point. Once you’ve got those working and understand them, then begin to think about making modifications. Also, you’ll have better luck with GNU Radio under GNU/Linux than under Windows. (You will have to use windows to compile any Verilog changes.) We do provide precompiled verilog in svn and the tarballs. Eric ---
**Author:** ![pankaj\_kumar](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/34f0e0/32.png) [@pankaj\_kumar](https://www.ruby-forum.com/u/pankaj_kumar)\ **Post date:** [September 25, 2007, 11:06pm UTC](https://www.ruby-forum.com/t/usrp-programming-the-fpga/86868/4 "2007-09-25T23:06:39Z")
On Mon, Feb 26, 2007 at 08:21:10AM -0800, pankaj kumar wrote: > the code which you have suggested, how to get that…? > > usrp\_fft.py > > where i am supposed to get this one… > > pankaj First off, download the GNU Radio code. Start here: [http://gnuradio.org/trac/wiki](http://gnuradio.org/trac/wiki) It’s in gnuradio-examples/python/usrp/usrp\_fft.py Eric ---
**Author:** ![pankaj\_kumar](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/34f0e0/32.png) [@pankaj\_kumar](https://www.ruby-forum.com/u/pankaj_kumar)\ **Post date:** [February 26, 2007, 5:59pm UTC](https://www.ruby-forum.com/t/usrp-programming-the-fpga/86868/5 "2007-02-26T17:59:23Z")
Hello, All: I am running the following small program which generate a periodical signal using vectors. I got Segmentation Fault, as shown in the following: # ======================================================================== lx@lx-desktop:sudo ./Signal3.py Blocked waiting for GDB attach (pid = 7714) Press Enter to continue: Sample rate = 8M Signal will generated by : A: Flex 2400 Tx Carrier : 2.468G Press Enter to quit : uUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUuUSegmentation fault Could anyone give any suggestion on how to trace the bug or why it happens? BTW, I tried to use gdb, whenver I do “(gdb) attach PID” the program stops running, it resumes until I quit from gdb. Thank you for your input. xin # The python program #!/usr/bin/env python from gnuradio import gr from gnuradio import usrp from gnuradio import eng\_notation import os print ‘Blocked waiting for GDB attach (pid = %d)’ % (os.getpid(),) raw\_input ('Press Enter to continue: ') def build\_graph (carrier=2.462e9): interp = 16 duc0 = 5e6 # IF frequency nchan = 1 fg = gr.flow\_graph () dest = usrp.sink\_c (0, interp, nchan) sample\_rate = dest.dac\_freq() / interp print "Sample rate = ", eng\_notation.num\_to\_str (sample\_rate) dest.set\_tx\_freq (0, duc0) dest.set\_pga(0,20) max = (2\*\*15)-1 min = -max vector = [] for i in range(40): vector.append(complex(max,max)) vector.append(complex(max,min)) vector.append(complex(min,max)) vector.append(complex(min,min)) for i in range(60): vector.append(complex(0,0)) src = gr.vector\_source\_c(vector,True) fg.connect (src, dest) dboard = usrp.selected\_subdev(dest, (0,0)) print “Signal will generated by :”, dboard.side\_and\_name() rf = dest.tune(dboard.\_which, dboard, carrier) if rf: print “Carrier :”, eng\_notation.num\_to\_str(rf.baseband\_freq) else: print “The range of the daugtherboard’s frequency is :”, eng\_notation.num\_to\_str(dboard.freq\_range()[0]), “-”, eng\_notation.num\_to\_str(dboard.freq\_range()[1]) raise SystemExit return fg if **name** == ‘ **main** ’: mygraph = build\_graph () mygraph.start () raw\_input ("Press Enter to quit : ") mygraph.stop () ---
**Author:** ![AxelCalhoun](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/a/3bc359/32.png) [@AxelCalhoun](https://www.ruby-forum.com/u/AxelCalhoun)\ **Post date:** [August 13, 2021, 10:46am UTC](https://www.ruby-forum.com/t/usrp-programming-the-fpga/86868/6 "2021-08-13T10:46:35Z")
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