# USRP N210 Clock generation

**URL:** <https://www.ruby-forum.com/t/usrp-n210-clock-generation/231144>\
**Category:** GNU Radio\
**Created:** [July 23, 2014, 6:57pm UTC](https://www.ruby-forum.com/t/usrp-n210-clock-generation/231144 "2014-07-23T18:57:51Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![addis\_a](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/a/c4cdca/32.png) [@addis\_a](https://www.ruby-forum.com/u/addis_a)\
**Post date:** [July 23, 2014, 6:57pm UTC](https://www.ruby-forum.com/t/usrp-n210-clock-generation/231144/1 "2014-07-23T18:57:51Z")

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* * *

Discuss-gnuradio mailing list  
removed\_email\_address@domain.invalid  
[https://lists.gnu.org/mailman/listinfo/discuss-gnuradio](https://lists.gnu.org/mailman/listinfo/discuss-gnuradio)

---

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**Author:** ![YarlagaddaS\_Anusha\_S](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/y/2acd7d/32.png) [@YarlagaddaS\_Anusha\_S](https://www.ruby-forum.com/u/YarlagaddaS_Anusha_S)\
**Post date:** [July 23, 2014, 8:08pm UTC](https://www.ruby-forum.com/t/usrp-n210-clock-generation/231144/2 "2014-07-23T20:08:11Z")

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HI Anusha,

this is the wrong mailing list for this – for your replies, I think  
it’s best to join [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid) [1] and continue this  
discussion there; I will crosspost my answer.

On 23.07.2014 18:56, Yarlagadda, Anusha (337G) wrote:

> Hi,  
> I am using URSPN210 series, have few questions regarding the clocking schemes  
> for this USRP N210. In the website, its mentioned USRP2 and N200/N210 have fixed  
> 100MHz clock which can’t be tuned and do not have option to use external clock.  
> You _can_ use an external clock, but it should be a 10MHz one.
> 
> We would like to use a different clock rate (49.2MHz) instead of the fixed  
> 100MHz that is generated from the Reference and system clock generation circuit(  
> I think all these clocks i.e fpga clock, TX/RX clock for the RF boaord ADC/DAC  
> clock are generated by the AD9510 that has on chip PLL core and multi ouput clock  
> distribution function).  
> I’m afraid that doesn’t fit the N210 design. You can’t use an arbitrary  
> clock rate – the idea is to decimate your signal to a integer fraction  
> of the master clock rate, and transport the signal at that sampling rate  
> to the host pc for further processing, e.g. resampling.

Furthermore, I’m a little curious what kind of system would preferably  
have a sampling rate of $49.2MHz/n, n \in [2,3,4,…]$ – please be  
aware that you can’t fit 49.2 MS/s of 16bit I+Q data through 1 Gigabit  
of ethernet!

> An external oscillator (U27 or external reference clock) is phase locked to a  
> reference input reference frequency clock of the AD9510.  
> In the USRP N210 FPGA Code can we program the divider values of AD9510 over the  
> SPI interface so that the output clock are not fixed?  
> As being said, the N210 design doesn’t really leave much room for this.
> 
> We would like to be compatible with our internal Radio waveform rates and  
> frequencies.  
> In this case, I recommend using a rational resampler on your host. GNU  
> Radio comes with some – you can try if you can match your desired  
> sampling rate with that.

With best regards,  
Marcus M.

[1] [http://lists.ettus.com/mailman/listinfo/usrp-users\_lists.ettus.com](http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com)