On Fri, Jul 28, 2006 at 10:01:11AM +0930, Daniel O’Connor wrote:
You can’t (as far as I can see) say to the SG engine that it’s reading from a
FIFO and it should treat the data as precious. Also there is no input to the
PLX chip to allow you to gate reads (ie a data available pin).
So if you wanted to use it you’d have to set up some local memory and then
copy data into that (from the FPGA) and then signal the host when a “page” is
done so it can program the PLX chip. Means you get an interrupt every page
which seems inefficient to me.
That’s why you want to use one one of the bus mastering PLX parts.
No host intervention in the tranfers after setting them up. You can
build a big S/G DMA chain, and only get an interrupt at the end, or
every N pages, or whatever.
Eric
On Friday 28 July 2006 15:29, Eric B. wrote:
So if you wanted to use it you’d have to set up some local memory and
then copy data into that (from the FPGA) and then signal the host when a
“page” is done so it can program the PLX chip. Means you get an interrupt
every page which seems inefficient to me.
That’s why you want to use one one of the bus mastering PLX parts.
No host intervention in the tranfers after setting them up. You can
build a big S/G DMA chain, and only get an interrupt at the end, or
every N pages, or whatever.
Yes, but you can’t use the built in S/G engine because it’s… limited.
The only way to enable/disable it is to program the DMA registers.
If the S/G engine is doing writes to PCI it wants to be the local bus
master -
that’s OK except that it may get an abort and will want to re-read some
data
so you have difficulty knowing for sure if it has truly finished with
the
data and you can throw it away.
To my mind that means you either copy the data into RAM on the card and
tell
the PC how many pages are available and it sets up the PLX chip, or you
use
the bus mastering capability and make your own SG engine.