# Something about xcvr2450 daughterboard **URL:** \ **Category:** GNU Radio\ **Created:** [December 8, 2011, 5:37am UTC](https://www.ruby-forum.com/t/something-about-xcvr2450-daughterboard/214641 "2011-12-08T05:37:12Z")\ **Posts on this page:** 2\ **Page:** 1
**Author:** ![luislavena](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/0ea827/32.png) [@luislavena](https://www.ruby-forum.com/u/luislavena)\ **Post date:** [December 8, 2011, 5:37am UTC](https://www.ruby-forum.com/t/something-about-xcvr2450-daughterboard/214641/1 "2011-12-08T05:37:12Z")
Dear everyone: Recently I am studying the codes about daughterboard xcvr2450(mainly usrp\host\lib\db\_xcvr2450.c) and there are some problems confuse me. 1. You see there are two steps in setting the frequency. First daughter board tunes as close as the target fequency and return the actual frequency . Second AD9862 perform the DUC procedure according to target fequency and actual frequency . But in function xcvr2450::set\_freq() the so called actual\_freq is set equal to target\_freq and the computing of actual\_freq is not used(there are // at the begining of the line). Why?? 2.Accoring to the table12 in the datasheet of MAX2829, we derive the divider ratio either using or .We should divide 20M.But it seems in function xcvr2450::set\_freq() 64M/3 is used to be divided instead of 20M.Why?? Any of your answers will be very appreciated.Thank you. ---
**Author:** ![signalswdm](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/s/f14d63/32.png) [@signalswdm](https://www.ruby-forum.com/u/signalswdm)\ **Post date:** [December 8, 2011, 6:03am UTC](https://www.ruby-forum.com/t/something-about-xcvr2450-daughterboard/214641/2 "2011-12-08T06:03:47Z")
On 12/07/2011 11:05 PM, signalswdm wrote: > 2.Accoring to the table12 in the datasheet of MAX2829, we derive the > [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid) > [Discuss-gnuradio Info Page](https://lists.gnu.org/mailman/listinfo/discuss-gnuradio) > You should probably be looking at the UHD version of the XCVR code, > since the “classic” stuff hasn’t been touched in over two years. The XCVR board has a reference divider on board, and it looks like it is (in UHD), always set to divide the incoming master clock by either 2 or 3, depending on the master clock. The reference clock going into the MAX2829 can be up to 40Mhz, according to the data sheet.