# Question about uhd fpga source

**URL:** <https://www.ruby-forum.com/t/question-about-uhd-fpga-source/210613>\
**Category:** GNU Radio\
**Created:** [August 12, 2011, 3:53am UTC](https://www.ruby-forum.com/t/question-about-uhd-fpga-source/210613 "2011-08-12T03:53:07Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![luislavena](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/0ea827/32.png) [@luislavena](https://www.ruby-forum.com/u/luislavena)\
**Post date:** [August 12, 2011, 3:53am UTC](https://www.ruby-forum.com/t/question-about-uhd-fpga-source/210613/1 "2011-08-12T03:53:07Z")

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Hi all,  
I have some problems when compile the fpga source.  
I open uhd-git\fpga\usrp1\toplevel\usrp\_std\usrp\_std.qpf with quartus II  
then compile meet a lot of errors which is the path error like that:  
Error (10054): Verilog HDL File I/O error at rx\_buffer.v(25): can’t open  
Verilog Design File “…/…/firmware/include/fpga\_regs\_common.v”  
when I fix the path problem then compile success. but the generated rbf  
file  
is different from the one in rbf directory.  
I use the newest git version.

Regards!

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**Author:** ![Page\_J](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/47e85d/32.png) [@Page\_J](https://www.ruby-forum.com/u/Page_J)\
**Post date:** [September 15, 2011, 3:32am UTC](https://www.ruby-forum.com/t/question-about-uhd-fpga-source/210613/2 "2011-09-15T03:32:02Z")

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Why no one have the answer or have the same question?

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**Author:** ![Page\_J](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/47e85d/32.png) [@Page\_J](https://www.ruby-forum.com/u/Page_J)\
**Post date:** [September 15, 2011, 3:38am UTC](https://www.ruby-forum.com/t/question-about-uhd-fpga-source/210613/3 "2011-09-15T03:38:11Z")

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On 14/09/11 09:31 PM, Page J. wrote:

> Why no one have the answer or have the same question?  
> 99.9% of the people on this list have no experience building the  
> firmware or making  
> modifications to it, they just use the as-supplied firmware.

The way the fpga code is setup, it’s intended to be built with “make”  
rather than the vendors  
IDE, so it doesn’t surprise me that you get topology-related errors.  
But that’s as much as I know.  
I’ve never built it myself.

Also, the way FPGA “routers” work, there’s a certain amount of  
Monte-Carlo decision making  
done in the way paths are laid out. So two different “runs” with  
exactly the same codebase  
can yield different (but functionally identical) FPGA binaries. The  
same thing happens with  
PCB routers–press the “route” button, it will be very often route the  
same circuit/physical placement  
with different lines.

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**Author:** ![Page\_J](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/p/47e85d/32.png) [@Page\_J](https://www.ruby-forum.com/u/Page_J)\
**Post date:** [September 15, 2011, 3:56am UTC](https://www.ruby-forum.com/t/question-about-uhd-fpga-source/210613/4 "2011-09-15T03:56:03Z")

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Marcus,  
thanks for your reply, the different build generate exactly the same  
binaries which just  
not the same with the binary in uhd git repo.