# Question about RFX2400 **URL:** \ **Category:** GNU Radio\ **Created:** [January 5, 2011, 3:28am UTC](https://www.ruby-forum.com/t/question-about-rfx2400/201310 "2011-01-05T03:28:09Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![luislavena](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/0ea827/32.png) [@luislavena](https://www.ruby-forum.com/u/luislavena)\ **Post date:** [January 5, 2011, 3:28am UTC](https://www.ruby-forum.com/t/question-about-rfx2400/201310/1 "2011-01-05T03:28:09Z")
Hi, I am testing a transceiver link in ISM band using two USRP2+RFX2400, one configured as TX and the other one as RX. I would like to test my own FPGA program, so for now I have your FPGA codes in which I only changed the signal driving the DAC in TX to be an square wave (+8191 or -8192) with frequency about 400Hz. At the RX side, I am looking (using an oscilloscope) at the input to the ADC and what I see is quite like my square wave modulated with a carrier of couple of MHz. I looked at the schematic of RFX2400 and I didn’t find any PLL or clock recovery circuitry! so I wonder how the frequency offset at RX could be avoided? Regards, Malihe ---
**Author:** ![Malihe\_A](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/898d66/32.png) [@Malihe\_A](https://www.ruby-forum.com/u/Malihe_A)\ **Post date:** [January 5, 2011, 3:39am UTC](https://www.ruby-forum.com/t/question-about-rfx2400/201310/2 "2011-01-05T03:39:25Z")
On Tue, 2011-01-04 at 19:25 -0700, Malihe A. wrote: > circuitry! so I wonder how the frequency offset at RX could be avoided? > > Regards, > Malihe In a software-defined radio, frequency estimation and clock recovery are typically done in software, to keep the hardware general-purpose enough for many different uses. You can either synchronize the two USRP2s by using a common 10MHz reference input to both devices (and enabling the reference lock), or deal with the inevitable frequency mismatch in software. –n ---
**Author:** ![Malihe\_A](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/898d66/32.png) [@Malihe\_A](https://www.ruby-forum.com/u/Malihe_A)\ **Post date:** [February 24, 2011, 3:14pm UTC](https://www.ruby-forum.com/t/question-about-rfx2400/201310/3 "2011-02-24T15:14:19Z")
Hi, I have included this line in my python flowgraph: |||sink.config\_mimo(usrp2.MC\_WE\_LOCK\_TO\_SMA) where sink is: ||sink ||=| |usrp2.sink\_32fc()| but I think USRP2 is not locked to the external reference clock since when I turn this ref clock generator off, there is no change in the spectrum of the output of USRP2. My understanding is that if USRP2 is locked to the ref clock, when I turn the clock off I should see no signal at the output of USRP2. can somebody please help me with this? How do I get the USRP2 to lock to the ref clock? Thanks, Malihe ---
**Author:** ![Malihe\_A](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/898d66/32.png) [@Malihe\_A](https://www.ruby-forum.com/u/Malihe_A)\ **Post date:** [February 24, 2011, 8:14pm UTC](https://www.ruby-forum.com/t/question-about-rfx2400/201310/4 "2011-02-24T20:14:19Z")
Yeah, I mean ref clock. I actually connect a 10MHz sin wave with 15dBm amplitude to two USRP2, one acting as TX and the other one acting as RX. the reason I am using this ref clock is to avoid the frequency offset between the TX and RX (I have been observing about 1MHz offset between the two). But yet there is about 1MHz frequency offset between TX and RX and that is the reason I thought their are not locked to the ref clock. Why would I still observe about 1MHz frequency offset then? ---
**Author:** ![Malihe\_A](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/898d66/32.png) [@Malihe\_A](https://www.ruby-forum.com/u/Malihe_A)\ **Post date:** [February 24, 2011, 8:31pm UTC](https://www.ruby-forum.com/t/question-about-rfx2400/201310/5 "2011-02-24T20:31:15Z")
On Wed, 2011-02-23 at 19:08 -0700, Malihe A. wrote: > Yeah, I mean ref clock. I actually connect a 10MHz sin wave with 15dBm > amplitude to two USRP2, one acting as TX and the other one acting as RX. > the reason I am using this ref clock is to avoid the frequency offset > between the TX and RX (I have been observing about 1MHz offset between > the two). But yet there is about 1MHz frequency offset between TX and RX > and that is the reason I thought their are not locked to the ref clock. > Why would I still observe about 1MHz frequency offset then? Dumb question, but are you syncing the source USRP2 (using config\_mimo) as well? Incidentally, 1MHz of offset at 2.4GHz is \>400ppm, which is a lot more frequency offset than I’d expect from two USRP2s tuned to the same frequency. Can you post your source and sink flowgraphs? –n