# Mainlining FPGA modifications **URL:** \ **Category:** GNU Radio\ **Created:** [June 8, 2011, 1:12am UTC](https://www.ruby-forum.com/t/mainlining-fpga-modifications/208002 "2011-06-08T01:12:09Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![dubstep](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/d/cdc98d/32.png) [@dubstep](https://www.ruby-forum.com/u/dubstep)\ **Post date:** [June 8, 2011, 1:12am UTC](https://www.ruby-forum.com/t/mainlining-fpga-modifications/208002/1 "2011-06-08T01:12:09Z")
Hi all, On Sat, May 28, 2011 at 21:30, Alexander C. [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid) wrote: > > > > > To make it more clear - we intend to keep all VRT/UHD related FPGA > code in place and just replace/change interaction with RF part. May be > we’ll have to slightly extend VRT/UHD code for our specific purposes, > but it will be minor changes. > > In other words - all our changes will be to support a new platform > seamlessly with existing UHD code. Could anyone comment on this topic after all? Tom, Josh, Philip - I’m not sure who should I bug about this? PS I’ve changed subject to a more meaningful. Sorry for messed subject line in the original e-mail. – Regards, Alexander C… ---
**Author:** ![alcost](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/a/4da419/32.png) [@alcost](https://www.ruby-forum.com/u/alcost)\ **Post date:** [June 9, 2011, 11:05pm UTC](https://www.ruby-forum.com/t/mainlining-fpga-modifications/208002/2 "2011-06-09T23:05:54Z")
On 06/07/2011 04:09 PM, Alexander C. wrote: > > > > We’ve started a project to implement a custom SDR hardware (which we > > > > but maintaining compatibility with the > > > > seamlessly with existing UHD code. > > Could anyone comment on this topic after all? > Tom, Josh, Philip - I’m not sure who should I bug about this? We are always looking for contributions to the FPGA code and will consider including any interesting new functionality. Matt ---
**Author:** ![alcost](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/a/4da419/32.png) [@alcost](https://www.ruby-forum.com/u/alcost)\ **Post date:** [June 10, 2011, 12:25am UTC](https://www.ruby-forum.com/t/mainlining-fpga-modifications/208002/3 "2011-06-10T00:25:05Z")
On Thu, Jun 9, 2011 at 21:19, Matt E. [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid) wrote: > > > > > > > > > > > > > I can’t answer the questions about where to best place the code in the tree, > > > > In other words - all our changes will be to support a new platform > > > > seamlessly with existing UHD code. > > > > Could anyone comment on this topic after all? > > Tom, Josh, Philip - I’m not sure who should I bug about this? > > We are always looking for contributions to the FPGA code and will > consider including any interesting new functionality. Is a new platform considered as an interesting functionality? And the main question - is there any guideline on how to add a new platform so that it will be possible to mainline it? – Regards, Alexander C.. ---
**Author:** ![alcost](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/a/4da419/32.png) [@alcost](https://www.ruby-forum.com/u/alcost)\ **Post date:** [June 10, 2011, 2:46am UTC](https://www.ruby-forum.com/t/mainlining-fpga-modifications/208002/4 "2011-06-10T02:46:10Z")
On Thu, Jun 9, 2011 at 2:01 PM, Alexander C. \< [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid)\> wrote: > > > > > > I’m not sure whether to post this to GnuRadio or to USRP-users, so I > > > > > > place our code and how to ensure our code will be accepted to the > > > > > > To make it more clear - we intend to keep all VRT/UHD related FPGA > > > > > > We are always looking for contributions to the FPGA code and will > > > > > > consider including any interesting new functionality. > > Is a new platform considered as an interesting functionality? > And the main question - is there any guideline on how to add a new > platform so that it will be possible to mainline it? > > – > Regards, > Alexander C.. As for where to put it, if it’s all being done open source, a service like github is great for this sort of thing. It makes it easy to track your changes and for everyone to see what’s going on. Then, it’s easy for us to take the code in afterwards. Since they provide the management and infrastructure as their business model, it’s a win for all of us. Tom ---
**Author:** ![alcost](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/a/4da419/32.png) [@alcost](https://www.ruby-forum.com/u/alcost)\ **Post date:** [June 10, 2011, 11:19am UTC](https://www.ruby-forum.com/t/mainlining-fpga-modifications/208002/5 "2011-06-10T11:19:16Z")
On Fri, Jun 10, 2011 at 04:41, Tom R. [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid) wrote: > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > integrate into > > > > – > > Regards, > > Alexander C.. > > As for where to put it, if it’s all being done open source, a service like > github is great for this sort of thing. It makes it easy to track your > changes and for everyone to see what’s going on. Then, it’s easy for us to > take the code in afterwards. Since they provide the management and > infrastructure as their business model, it’s a win for all of us. Yes, I know about github and that’s what we intend to use indeed. My question was more about where to put the code with respect to source code directory tree. But seems like there are no guidelines, so we’ll go the way we find convenient for us. – Regards, Alexander C..