# GSOC 14 project "Vector Network Analyzer" **URL:** \ **Category:** GNU Radio\ **Created:** [March 4, 2014, 6:38pm UTC](https://www.ruby-forum.com/t/gsoc-14-project-vector-network-analyzer/239557 "2014-03-04T18:38:03Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![musicdenotation](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/ea666f/32.png) [@musicdenotation](https://www.ruby-forum.com/u/musicdenotation)\ **Post date:** [March 4, 2014, 6:38pm UTC](https://www.ruby-forum.com/t/gsoc-14-project-vector-network-analyzer/239557/1 "2014-03-04T18:38:03Z")
Hi I am Mitul Vekariya [https://github.com/mitul93](https://github.com/mitul93) - final year student of Electronics and Communication (ECE) branch at Nirma University, India. I am very interested in mentioned project[http://gnuradio.org/redmine/projects/gnuradio/wiki/GSoC](http://gnuradio.org/redmine/projects/gnuradio/wiki/GSoC) . I like digital signal processing, Embedded Linux, Digital Communication and RF designing. I didn’t work on any USRP devices, but I have experience of FPGA programming using VHDL and LabVIEW. I am familiar with SDR fundamentals and GNURadio. * * * Regarding Project, I’ve found one good document [http://www2.ee.cityu.edu.hk/~sklmmw/apmtt/B2BJan14/day1/Agilent\_VNA\_AN\_Basics\_5965-7917E.PDF](http://www2.ee.cityu.edu.hk/~sklmmw/apmtt/B2BJan14/day1/Agilent_VNA_AN_Basics_5965-7917E.PDF)from agilent. Summary of what I understood from that document: 1. Using usrp b210 I can generate pure tone sine wave as test signal 2. I will connect DUT ( device under test ) with external components to the usrp and measure transmitted and reflected signal 3. The amplitude and phase of the received signal will lead to different parameters How can we measure phase between two sine waves using FPGA? The method of zero crossing is advised or not? Please give you inputs on this project. Thanks Mitul Vekariya Institute of Technology Nirma University India ---
**Author:** ![MITUL\_VEKARIYA](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/57b2e6/32.png) [@MITUL\_VEKARIYA](https://www.ruby-forum.com/u/MITUL_VEKARIYA)\ **Post date:** [March 5, 2014, 12:10pm UTC](https://www.ruby-forum.com/t/gsoc-14-project-vector-network-analyzer/239557/2 "2014-03-05T12:10:59Z")
Hi, Thanks for reply. I want to measure phase between reference signal and signal coming from DUT(Device Under Test). It may possible that due to non-linear characteristic of the device, there are changes in frequency and amplitude of signal. In this case the method you mentioned will give correct phase? Thanks Mitul Vekariya ---
**Author:** ![MITUL\_VEKARIYA](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/57b2e6/32.png) [@MITUL\_VEKARIYA](https://www.ruby-forum.com/u/MITUL_VEKARIYA)\ **Post date:** [March 5, 2014, 3:17am UTC](https://www.ruby-forum.com/t/gsoc-14-project-vector-network-analyzer/239557/3 "2014-03-05T03:17:22Z")
Hi, > How can we measure phase between two sine waves using FPGA? Supposing the two sine waves have the same frequency. For two discrete complex signals, v1 and v2. we can compute the phase difference as follow. v3 = v1 \* conj(v2) phase diff = arctan(imag(v3) , real(v3)) (conj() means conjugate) Best, Zhenhua 2014-03-05 1:36 GMT+08:00 MITUL VEKARIYA [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid): ---
**Author:** ![MITUL\_VEKARIYA](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/57b2e6/32.png) [@MITUL\_VEKARIYA](https://www.ruby-forum.com/u/MITUL_VEKARIYA)\ **Post date:** [March 5, 2014, 12:24pm UTC](https://www.ruby-forum.com/t/gsoc-14-project-vector-network-analyzer/239557/4 "2014-03-05T12:24:31Z")
Taking the average of all datas may works 🙂 Airprobe uses this method to calculate the phase difference. Best, Zhenhua 2014-03-05 19:09 GMT+08:00 MITUL VEKARIYA [removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid): ---
**Author:** ![MITUL\_VEKARIYA](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/57b2e6/32.png) [@MITUL\_VEKARIYA](https://www.ruby-forum.com/u/MITUL_VEKARIYA)\ **Post date:** [March 10, 2014, 6:14am UTC](https://www.ruby-forum.com/t/gsoc-14-project-vector-network-analyzer/239557/5 "2014-03-10T06:14:55Z")
Hi Martin Thanks for the reply. Right now I am preparing draft for proposal. As soon as I finish my draft I will upload it so that mentors can evaluate it. ---
**Author:** ![MITUL\_VEKARIYA](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/m/57b2e6/32.png) [@MITUL\_VEKARIYA](https://www.ruby-forum.com/u/MITUL_VEKARIYA)\ **Post date:** [March 5, 2014, 6:08pm UTC](https://www.ruby-forum.com/t/gsoc-14-project-vector-network-analyzer/239557/6 "2014-03-05T18:08:32Z")
On 04.03.2014 18:36, MITUL VEKARIYA wrote: > Hi > I am Mitul Vekariya [https://github.com/mitul93](https://github.com/mitul93) - final year student of > Electronics and Communication (ECE) branch at Nirma University, India. > I am very interested in mentioned project > [http://gnuradio.org/redmine/projects/gnuradio/wiki/GSoC](http://gnuradio.org/redmine/projects/gnuradio/wiki/GSoC). > I like digital signal processing, Embedded Linux, Digital Communication > and RF designing. > I didn’t work on any USRP devices, but I have experience of FPGA > programming using VHDL and LabVIEW. I am familiar with SDR fundamentals > and GNURadio. Mitul, look at the emails we sent out to the other GSoC applicants (go to the mailing list archive if necessary). You’ll need to start working on a proposal. Also, for this project, you’ll need to make sure we know you know what you’re doing from a signal processing perspective. M