# Costum FPGA in E310 **URL:** \ **Category:** GNU Radio\ **Created:** [April 11, 2015, 7:53pm UTC](https://www.ruby-forum.com/t/costum-fpga-in-e310/241521 "2015-04-11T19:53:18Z")\ **Posts on this page:** 3\ **Page:** 1
**Author:** ![Detlef\_R](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/d/58f4c7/32.png) [@Detlef\_R](https://www.ruby-forum.com/u/Detlef_R)\ **Post date:** [April 11, 2015, 7:53pm UTC](https://www.ruby-forum.com/t/costum-fpga-in-e310/241521/1 "2015-04-11T19:53:18Z")
Hi all, I am actually working on a project needs migrate an old FPGA program to E310. First, I want to custom the official FPGA program of E310. But I found some configurations of PS are not the same on the schematics diagram. And I tried to export to SDK, but even the simple hello world program didn’t work. I listed what I have done as follow: 1. first, I downloaded the FPGA source code from this address: [GitHub - EttusResearch/fpga at master](https://github.com/EttusResearch/fpga/tree/master) 2. I taped these commands to build the project: $source /opt/Xilinx/14.7/ISE\_DS/setting64.sh $export PATH=$PATH: /opt/Xilinx/14.7/ISE\_DS/ISE/bin/bin/lin64/xtclsh $cd fpga-master/usrp3/top/e300 $make E310 3. This step took about 1 hour. And then, I open the XPS project. $cd build-E310/zynq-ps $xps e300\_ps.xmp 4. The XPS was just opened. But from here I found some settings I dont understand. In the ZYNQ PS CONFIGURATION, the UART1 was selected using MIO 48 49, but in the schematic diagram of USRP E300 series Motherboard, the UART was using UART0. And UART0 used MIO 14 and MIO 15. 5. If I tried to generate the bitstream from this XPS project, it will give me a lot of errors like: ERROR:MapLib:979 - LUT6 symbol “axi\_interconnect\_1/axi\_interconnect\_1/mi\_protocol\_conv\_bank/gen\_protocol\_slot[0].gen\_prot\_conv.conv\_inst/gen\_axi3.axi3\_conv\_inst/USE\_READ.USE\_SPLIT.read\_addr\_inst/Madd\_M\_AXI\_AADDR\_I[31]\_GND\_19\_o\_add\_51\_OUT\_lut\<10\>” (output signal=axi\_interconnect\_1/axi\_interconnect\_1/mi\_protocol\_conv\_bank/gen\_protocol\_slot[0].gen\_prot\_conv.conv\_inst/gen\_axi3.axi3\_conv\_inst/USE\_READ.USE\_SPLIT.read\_addr\_inst/Madd\_M\_AXI\_AADDR\_I[31]\_GND\_19\_o\_add\_51\_OUT\_lut\<10\>) has input signal “axi\_interconnect\_1/axi\_interconnect\_1/mi\_protocol\_conv\_bank/gen\_protocol\_slot[0].gen\_prot\_conv.conv\_inst/gen\_axi3.axi3\_conv\_inst/USE\_READ.USE\_SPLIT.read\_addr\_inst/S\_AXI\_AADDR\_Q\<10\>” which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. 1. Finally, I exported design to SDK with no bitstream, but even the simple Hello world print program didn’t work. There was nothing output from the UART port. I want know if there is someone have done a similar work who can tell me where am I doing wrong? Thanks, Weidong Wang ---
**Author:** ![casper\_the\_ghost](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/c/58956e/32.png) [@casper\_the\_ghost](https://www.ruby-forum.com/u/casper_the_ghost)\ **Post date:** [April 12, 2015, 8:05pm UTC](https://www.ruby-forum.com/t/costum-fpga-in-e310/241521/2 "2015-04-12T20:05:40Z")
Hi Weidong, the XPS project that’s made during the current E310 build is not meant to be used to implement custom designs. We usually just add stuff to the Makefiles (custom RTL, coregen files, etc). If you can give us some more info on what you’re trying to do, we’ll be able to help you out better. Cheers, Moritz On Sat, Apr 11, 2015 at 10:41 AM, linux ---
**Author:** ![casper\_the\_ghost](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/c/58956e/32.png) [@casper\_the\_ghost](https://www.ruby-forum.com/u/casper_the_ghost)\ **Post date:** [April 16, 2015, 10:43am UTC](https://www.ruby-forum.com/t/costum-fpga-in-e310/241521/3 "2015-04-16T10:43:19Z")
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