# Arbitrary ADC resolution at the receiver

**URL:** <https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706>\
**Category:** GNU Radio\
**Created:** [June 30, 2014, 4:38pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706 "2014-06-30T16:38:45Z")\
**Posts on this page:** 7\
**Page:** 1

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**Author:** ![addis\_a](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/a/c4cdca/32.png) [@addis\_a](https://www.ruby-forum.com/u/addis_a)\
**Post date:** [June 30, 2014, 4:38pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706/1 "2014-06-30T16:38:45Z")

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Hello everyone,

I excuse myself on advance by my noob question…

I have an N210 with an SBX front end, and I want to experiment with  
decoding signals at a lower resolution, rather than the default 12 bits  
provided by the N210 ADCs. Does anyone know if (and how) can I limit the  
resolution of the ADCs arbitrarily?

I am aware that I can reduce the resolution afterwards, mapping the  
signals  
to a lower resolution in base band, but I’d really like to do that  
before  
the DDC at the FPGA.

Cheers to everyone!

Leonardo S. Cardoso  
removed\_email\_address@domain.invalid

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**Author:** ![leonardocg](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/e274bd/32.png) [@leonardocg](https://www.ruby-forum.com/u/leonardocg)\
**Post date:** [June 30, 2014, 4:45pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706/2 "2014-06-30T16:45:19Z")

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* * *

Discuss-gnuradio mailing list  
removed\_email\_address@domain.invalid  
[https://lists.gnu.org/mailman/listinfo/discuss-gnuradio](https://lists.gnu.org/mailman/listinfo/discuss-gnuradio)

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**Author:** ![leonardocg](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/e274bd/32.png) [@leonardocg](https://www.ruby-forum.com/u/leonardocg)\
**Post date:** [June 30, 2014, 4:47pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706/3 "2014-06-30T16:47:42Z")

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The n200 and n210 have 14 bit ADCs.

In any case, you can fake fewer bits by zeroing the low order bits in  
the  
fpga.

Matt

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<div class="post-metadata">

**Author:** ![leonardocg](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/e274bd/32.png) [@leonardocg](https://www.ruby-forum.com/u/leonardocg)\
**Post date:** [June 30, 2014, 5:01pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706/4 "2014-06-30T17:01:25Z")

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Yes, 14 bits… mistyped the ADC resolution…

Thanks, Matt. I’ll investigate this idea…

Leonardo S. Cardoso  
removed\_email\_address@domain.invalid

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**Author:** ![leonardocg](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/e274bd/32.png) [@leonardocg](https://www.ruby-forum.com/u/leonardocg)\
**Post date:** [July 1, 2014, 2:55pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706/5 "2014-07-01T14:55:52Z")

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Hi Marcus,

There are several reasons why we would like to avoid reducing the  
resolution in software: 1. Reduce receiver complexity; 2. Capture any  
artifact of the DDC with respect to the reduction of the resolution.

Frankly speaking, I’m not sure any of these arguments are defendable to  
impose a resolution control at the ADC or even the ADC-FPGA interface.  
If  
it isn’t, then I agree it is much simple to do it in soft.

BR,

Leo

Leonardo S. Cardoso  
removed\_email\_address@domain.invalid

On Mon, Jun 30, 2014 at 5:46 PM, Marcus Müller  
[removed\_email\_address@domain.invalid](mailto:removed_email_address@domain.invalid)

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<div class="post-metadata">

**Author:** ![leonardocg](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/e274bd/32.png) [@leonardocg](https://www.ruby-forum.com/u/leonardocg)\
**Post date:** [July 1, 2014, 3:42pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706/6 "2014-07-01T15:42:56Z")

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Hi Leo,

well, I’d argue that reducing receiver complexity doesn’t really happen  
when you start changing the FPGA with respect to dev effort; I can see  
your DDC numerical accuracy point, though.  
However, how would reducing the ADC resolution make artifacts more  
noticable? As you get ca -6dB theoretical SNR with each bit you cut at  
the ADC, errors in the DDC should become less relevant, not more.

Best Regards,  
Marcus

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<div class="post-metadata">

**Author:** ![leonardocg](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/l/e274bd/32.png) [@leonardocg](https://www.ruby-forum.com/u/leonardocg)\
**Post date:** [June 30, 2014, 5:47pm UTC](https://www.ruby-forum.com/t/arbitrary-adc-resolution-at-the-receiver/230706/7 "2014-06-30T17:47:54Z")

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Just out of curiosity: Why would you want to reduce the ADC resolution?  
Most of the effects introduced can be simulated in GNU Radio, e.g. by  
converting a float stream to integer and dividing it by a constant power  
of two.

Greetings,  
Marcus
