# \[ANN\] Ruby-VPI 21.1.0

**URL:** <https://www.ruby-forum.com/t/ann-ruby-vpi-21-1-0/144844>\
**Category:** Ruby\
**Created:** [August 3, 2008, 12:28am UTC](https://www.ruby-forum.com/t/ann-ruby-vpi-21-1-0/144844 "2008-08-03T00:28:05Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![snk](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/s/d9b06d/32.png) [@snk](https://www.ruby-forum.com/u/snk)\
**Post date:** [August 3, 2008, 12:28am UTC](https://www.ruby-forum.com/t/ann-ruby-vpi-21-1-0/144844/1 "2008-08-03T00:28:05Z")

</div>

Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI  
and a platform for unit testing, rapid prototyping, and  
systems integration of Verilog modules through Ruby. It  
lets you create complex Verilog test benches easily and  
wholly in Ruby.

```
         http://ruby-vpi.rubyforge.org

```

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HTML version of this release announcement is available here:  
[http://snk.rubyforge.org/web/2008-08-02-ruby-vpi-21-1-0.html](http://snk.rubyforge.org/web/2008-08-02-ruby-vpi-21-1-0.html)

Ruby-VPI 21.1.0

Contents

• 1 Features  
• 2 Improvements

This release adds new compilation hooks, improves support  
for Mentor Modelsim, simplifies the internal task  
scheduler, and shortens the critical path of the C  
extension.

1 Features

• Added CFLAGS\_EXTRA and LDFLAGS\_EXTRA environment  
variables, which allow you to append to the default  
CFLAGS and LDFLAGS with which your Ruby installation  
was built.

Note that the CFLAGS and LDFLAGS environment variables  
still behave the same way: they completely override the  
defaults.

2 Improvements

• Attempted to fix spurious failures with Modelsim 6.2g  
by advancing to the same time step[1] before applying  
cache write operations.

• Replaced thread-based tasks with continuations (callcc)  
in internal scheduler.

• Avoid some function calls on the C extension’s critical  
path by storing/reusing return values.

[1] How can advancing the simulator by zero time steps solve  
anything?

A time step is really composed of multiple time slots, so  
advancing by zero time steps could, in fact, take us to any  
future time slot withnin the current time step.

There are more details that I don’t care to explain here,  
but in general, this technique seems to cure Modelsim 6.2g  
by advancing it into a time slot where write operations can  
be applied correctly.