# \[ANN\] Ruby-VPI 18.0.0

**URL:** <https://www.ruby-forum.com/t/ann-ruby-vpi-18-0-0/110940>\
**Category:** Ruby\
**Created:** [August 1, 2007, 7:47am UTC](https://www.ruby-forum.com/t/ann-ruby-vpi-18-0-0/110940 "2007-08-01T07:47:28Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![snk](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/s/d9b06d/32.png) [@snk](https://www.ruby-forum.com/u/snk)\
**Post date:** [August 1, 2007, 7:47am UTC](https://www.ruby-forum.com/t/ann-ruby-vpi-18-0-0/110940/1 "2007-08-01T07:47:28Z")

</div>

Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI  
and a platform for unit testing, rapid prototyping, and  
systems integration of Verilog modules through Ruby. It  
lets you create complex Verilog test benches easily and  
wholly in Ruby.

• See [http://ruby-vpi.rubyforge.org](http://ruby-vpi.rubyforge.org) for details.

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Version 18.0.0 (2007-07-31)

This release restores support for Synopsys VCS and Cadence  
NC-Sim, improves portability and performance, and enhances  
the VPI abstraction layer.

Thanks

• Calvin Wong discovered how to bypass the following  
error emitted by Synopsys VCS when loading the Ruby-VPI  
shared object file.

```
  Could not open library specified in -load option obj/vcs
  obj/vcs: undefined symbol: vpi_put_data

```

Caution

• SWIG is now required in order to compile and install  
Ruby-VPI.

• Vpi::Handle.put\_value no longer checks whether the  
value written matches the value read back after writing  
because that only works when there is no VPI delay  
associated with the write.

• When Vpi::Handle.put\_value is used to write a value to  
a wire (VpiNet), it now forces the value. This is done  
to ensure portability:

```
Synopsys VCS and Cadence NC-Sim forget the value
written to a wire during the next simulation time step,
whereas Mentor Modelsim and GPL Cver remember the value
(thereby treating wires as registers).

Note that you have to release a forced value (using
Vpi::Handle.release_value) on a wire after writing to
the wire if you want the design under test have the
ability to update the value of the wire later on:

  your_wire.intVal = 15
  your_wire.release_value
  advance_time # let the Verilog DUT modify your_wire

In addition, you can check if a wire has a forced value
using the Vpi::Handle.value_forced? method.

```

• If the format is not specified, Vpi::Handle.get\_value  
now assumes that you want to read the value in  
VpiIntVal format (because this is the most common  
case).

• The definition of “Derivatives” has been reworded for  
clarity in the project license.

Repairs

• Synopsys VCS and Cadence NC-Sim simulators now  
correctly load Ruby-VPI. Also, the 64-bit versions of  
these simulators are now supported.

Improvements

• Added “force\_value”, “release\_value”, and  
“value\_forced?” methods to the Vpi::Handle class.

• Vpi::Handle.put\_value now tries to automatically detect  
the format of the value to be written. As a result, you  
can now write your\_handle.put\_value 35 in lieu of  
writing your\_handle.intVal = 35.

• Vpi::Handle.inspect now shows the hexStrVal of the  
handle (because it is a common case to want to see a  
handle’s logic value along with its other information).

• Added method caching (memoizing) for VPI property  
accesses on handles.