# \[ANN\] Ruby-VPI 10.0.0

**URL:** <https://www.ruby-forum.com/t/ann-ruby-vpi-10-0-0/74349>\
**Category:** Ruby\
**Created:** [November 5, 2006, 9:33am UTC](https://www.ruby-forum.com/t/ann-ruby-vpi-10-0-0/74349 "2006-11-05T09:33:41Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![snk](https://www.ruby-forum.com/letter_avatar_proxy/v4/letter/s/d9b06d/32.png) [@snk](https://www.ruby-forum.com/u/snk)\
**Post date:** [November 5, 2006, 9:33am UTC](https://www.ruby-forum.com/t/ann-ruby-vpi-10-0-0/74349/1 "2006-11-05T09:33:41Z")

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Version 10.0.0 (2006-11-05)

Ruby-VPI is a Ruby interface to Verilog VPI. It lets you create  
complex Verilog test benches easily and wholly in Ruby.

Website: [http://ruby-vpi.rubyforge.org](http://ruby-vpi.rubyforge.org)

Install: gem install ruby-vpi

Summary

This release adds the ability to access a handle’s children  
and reduces the amount of code produced by the automated  
test generator.

Acknowledgment

Thanks to Matt Fischler for finding the problem of  
misdirected compilation errors in Verilog benches.

Notice

• The way in which Ruby-VPI and generated tests interact  
has changed: the design is now a VPI handle object and  
the design.rb and proto.rb files define singleton  
methods for that object.  
â–¡ I suggest that you regenerate your existing tests  
(just run generate\_test.rb again) whilst employing  
the service of a text merging tool (see the user  
manual).

• You can now access a handle’s children by simply  
calling methods on it. In the event that a child handle  
has the same name as a VPI property, the child is given  
priority. However, you can always access VPI properties  
explicitly via the get\_value and put\_value methods.

• generate\_test.rb no longer accepts the -s and -u  
options. Use their longer counterparts --rspec and  
–xunit instead.

Detail

Automated test generator

• Generated Verilog benches no longer divert compilation  
errors from Verilog design files. That is, if the  
Verilog simulator finds compilation errors in a Verilog  
design file, it will report that the Verilog design  
file is at fault (instead of reporting that the  
generated Verilog bench is at fault).

• The user is now notified when a backup of an existing  
file is made.

• Generated tests have been greatly simplified to reduce  
the amount of work for the user.  
â–¡ The design is now just a handle to the module in  
the Verilog bench.  
â–¡ include Vpi and @design are no longer generated.  
â–¡ The tutorial and examples have been updated  
accordingly.

User manual

• Revised the stylesheet to make disjoint sections  
readily distinguishable from eachother, through  
generous spacing and minor coloring.

• Added tips about ruby-vpi/runner\_proxy, rake -T, and  
using kdiff3 with generate\_test.rb.

• Moved installation information into a new “setup”  
chapter.