I was trying to recompile the usrp_std.v just to try out the tools,
since we plan to
make future changes to the FPGA. However only Quartus II v6.1 is
available on
the Altera website. It compiles and synthesizes fine, but it ends up
with
15501 blocks of type logic cell which just won’t fit into the 12060
block EP1C12Q240C8N.
Is there a compile setting that needs to be set or something edited in
the source
to get the logic cell size down so it will fit into the USRP FPGA?
Thanks
Jim Murashige, Rosum
On Fri, Jan 05, 2007 at 06:36:42PM -0800, Jim Murashige wrote:
block EP1C12Q240C8N.
Jim Murashige, Rosum
Hi Jim,
This is news to me. Did you use our project file? If so, this sounds
like a regression in Quartus. Last time I built everything I used
Quartus 6.0sp1. I suggest sending email to somebody at Altera and
asking for a link to the earlier version.
Eric
Jim Murashige wrote:
block EP1C12Q240C8N.
Is there a compile setting that needs to be set or something edited in
the source
to get the logic cell size down so it will fit into the USRP FPGA?
I had no problem with nuilding a freshly-checked out version on Quartus
6.1. It came to 11,100 logic elements, 92% full.
Matt