Forum: GNU Radio Setting up clock synchronization blocks

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Hi Nemanja,

I remember having some trouble with this, as well, but I can't quite
remember the details.

However, since you're using a pretty long preamble, have you tried
using that for sync? The problem with M&M is that the output of the
phase demodulator is quite 'soft', so accurate syncing is difficult in
any case. Using the preamble makes it much easier; if you start with an
oversampling rate of 4 you don't even need to do any polyphase-stuff.

MB

On Mon, Feb 18, 2013 at 05:23:04PM +0100, Nemanja Savic wrote:
>
>
>
> Many regardsInline image 1
>
>
> --
> Nemanja Savić
>



> _______________________________________________
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--
Karlsruhe Institute of Technology (KIT)
Communications Engineering Lab (CEL)

Dipl.-Ing. Martin Braun
Research Associate

Kaiserstraße 12
Building 05.01
76131 Karlsruhe

Phone: +49 721 608-43790
Fax: +49 721 608-46071
www.cel.kit.edu

KIT -- University of the State of Baden-Württemberg and
National Laboratory of the Helmholtz Association

Hi,

Martin, what exactly do you mean by:


> However, since you're using a pretty long preamble, have you tried
> using that for sync?


Preamble is indeed long. On the figure I attached in my first post it 
can
be seen the input and output od
synchronization M&M block. I am expecting this block to do 
synchronization
based on preamble.
In worst case I can meassure every pulse and make my own synchronizator,
which looks a bit ugly, but
works.

If you start with an oversampling rate of 4 you don't even need to do 
any
> polyphase-stuff.
>

Not quite sure that I understand, but I am sampling signal with ca. 
500k,
and symbol rate is 19.2k, so if you were thinking about oversampling 
after
bit slicer, yes i have oversampling of ca. 25.

In my receiver, after a bit filtered demodulated signal from quadrature 
FM
demodulator, I have a block, designed by myself, that does bit slicing. 
It
is basically simulation of a circuit that is used in
some receivers with min and max diode detector circuits. Since I am 
quite
sure this is not the usual way of doing this, how am I supposed to get
digital
pulses from demodulated signal.

Best

On Thu, Feb 21, 2013 at 02:10:24PM +0100, Nemanja Savic wrote:
> Preamble is indeed long. On the figure I attached in my first post it can be
> seen the input and output od
> synchronization M&M block. I am expecting this block to do synchronization
> based on preamble.

Your packet sync, but not your clock sync (how would the M&M even know
about your preamble?).

> Not quite sure that I understand, but I am sampling signal with ca. 500k, and
> symbol rate is 19.2k, so if you were thinking about oversampling after bit
> slicer, yes i have oversampling of ca. 25.

Yeah, that's probably over the top. Filter and decimate, that saves
clock cycles and possibly improves your SNR.

> In my receiver, after a bit filtered demodulated signal from quadrature FM
> demodulator, I have a block, designed by myself, that does bit slicing. It is
> basically simulation of a circuit that is used in
>
> some receivers with min and max diode detector circuits. Since I am quite sure
> this is not the usual way of doing this, how am I supposed to get digital
> pulses from demodulated signal.

I recommend parsing gr-digital/python/gmsk.py for an idea how this could
be done (though, granted, that doesn't work perfect either, but also
doesn't sync via preamble).

MB

--
Karlsruhe Institute of Technology (KIT)
Communications Engineering Lab (CEL)

Dipl.-Ing. Martin Braun
Research Associate

Kaiserstraße 12
Building 05.01
76131 Karlsruhe

Phone: +49 721 608-43790
Fax: +49 721 608-46071
www.cel.kit.edu

KIT -- University of the State of Baden-Württemberg and
National Laboratory of the Helmholtz Association

Hi,

thaks again Martin, I will take a look at the block you suggested.

What I meant before, is that I was expecting that M&M block will
tune it's internall coefficients ,or whatever, based on preamble that 
comes,
since that should be the purpose of the preamble (like in hardware
receivers).

The structure of my receiver is more or less copied one from 
gfsk_loopback.
But in that block, output of demodulator is connected to the M&M. In my 
case
I provide M&M with pure digital signal, which should make things better 
in
the meaning of finding correct edges.

A the moment, M&M has 100% successful preamble detection, but then it
starts to stuff some bits which make
message incorrect.

Best
Nemanja

Hi all again,

I basically did what Martin suggested, after demodulation I lowered
sampling rate from 500k to 100k. Just to make brief reminding, I am 
working
on a
FSK receiver, working in 434MHz ISM band, symbol rate is 19.2kbps and 
used
modulation is FSK.
After making decimation, the number of samples per symbol within M&M 
sync
block changed, from previous 26 to 5. When I made this change M&M stoped
working properly, and packed demod is unable to detect preamble. I would
like to ask if somebody can explain me the way to tune this block, I 
don't
think
making 5 sliders and just changing values would be the solution, and 
there
must be some logical way to do that.

Best
Nemanja

Any suggestions on my problem guys?