Forum: GHDL Re: new to GHDL - port / signal question

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Le mardi 16 juin 2009 à 07:29 +0000, Alex Huntley a écrit :
> It's not because you're connecting a "std_logic" type to a "bit" type
> is it?
Yes it can be that, Ghdl output this error for this kind of mistake.

Thanks everyone!  The problem was assigning a "BIT" type input port
signal to a "STD_LOGIC" signal.  I really appreciate the assistance, I
was going crazy trying to figure it out, the error message GHDL output
for that didn't cause me to think of a type mismatch.  I'm really
enjoying learning VHDL, and ghdl is brilliant!
Chris