USRP2 Simultaneous Tx and Rx Transmit Errors

GNU Radio
1

Hello all,

When I try to simultaneously transmit and receive a sine wave source
on one USRP2 using GRC, there appear to be phase discontinuities in
the transmitted waveform(as if packets from the computer to the usrp2
for transmit are possibly being lost or garbled). This only occurs
when transmitting and receiving at the same time, and when I connected
the tx signal to a spectrum analyzer it showed random spurs in
addition to the expected peak from the signal. When only transmitting
the output on a spectrum analyzer confirms that the transmits properly
and when receiving a signal from a signal generator there are no
errors. This occurred even when the decimation and interpolation rate
was set to 512 and I tried a different ethernet cable but the problem
still persists.

Here’s my setup:
GNU Radio rev. 10661 running on Ubuntu 8.04
Dell E6400 Laptop with P9500 processor (2.53GHz) and 4Gb RAM
1 USRP2 with LFRX and LFTX daughtercards, firmware released 3/15
USRP2 Connected directly to laptop (no router/switch)

I’ve attached the GRC graph and some examples of a Scope display.

If anyone has similar problems or has any ideas how to solve this,
please let me know. Also, if you can do this without the error let me
know, maybe the issue comes from the laptop.

Thanks,
Kyle

2

On Wed, Mar 25, 2009 at 01:13:32PM -0700, Johnathan C. wrote:

and when receiving a signal from a signal generator there are no
errors. This occurred even when the decimation and interpolation rate
was set to 512 and I tried a different ethernet cable but the problem
still persists.

Kyle,

Matt made some changes in the USRP2 FPGA and firmware code in
changeset 10762 that we believe fixes this problem.

Can you please download and try the lastest FPGA image and firmware
from http://gnuradio.org/releases/usrp2-bin/trunk and let us know if
this fixes it for you.

FYI, at high data rates, full-duplex, the firmware becomes a
bottleneck and will limit the maximum reliable throughput
achievable. Fixing that will most like require moving at least some
of the state machine that’s currently implemented by firmware into the
FPGA fabric.

Eric

3

of the state machine that’s currently implemented by firmware into the
FPGA fabric.

Eric

I tested the new FPGA and firmware changes and everything seems to
work well down to a decimation and interpolation of 28.

Thanks for the fix!
Kyle