We want to make several standalone transmitters which transmit OFDM signals synchronized with 1pps signal and external 10MHz closk using USRP2. We want to implement the transmitters using FPGA, while daughter board parameters and interpolation rate are fixed. We will transmit "frames" which consist of preamble and fixed many data OFDM symbols. We want to ask following questions about above. 1. Where does the "making frame block" connect with? 2. What block may be deleted for elmenating corresponding GNU radio block? 3. How do we modify the FPGA and/or firmware for fixing parameters (interpolation rate, center frequency, etc.) 4. We may have to eliminate receiving buffer cause of shortage of memory. How can we delete it? 5. If exists, please send us the whole system block diagram. Thanks.
on 2009-02-13 11:50
on 2009-02-16 23:36
On Fri, Feb 13, 2009 at 10:50:54AM +0100, Yongsang K. wrote: > > 4. We may have to eliminate receiving buffer cause of shortage of > memory. > How can we delete it? > > 5. If exists, please send us the whole system block diagram. Your best bet is to take a look at the existing code. With regard to firmware, take a look at txrx.c and everything that it calls. All of the peripherals visible to the firmware are defined in memory_map.h. You can find data sheets for most of the wishbone peripherals under usrp2/fpga/opencores The top-level of the verilog is in usrp2/fpga/top/u2_rev3. If you're not connecting to the ethernet at all, you may be able to remove the entire buffer_pool abstraction. Ultimately you'll want to clock your samples into the Tx DSP pipeline. Eric