Forum: GHDL Cast makes the signal silently read only

Hi

I had a strange issue.

I am using matrixes defined as a vector of vectors rather than a multi
dimentional as I access always to a line/column at a time.

The code was like

type myTypeVector std_logic_vector( param_size - 1 downto 0 )
type myTypeVector( numberofitems - 1 downto 0 )
signal instanceMyTypeMatrix : myTypeMatrix


I defined somewehre else a component like

component
generic .....
port ( ... theOuput : out std_logic_vector( param_size - 1 downto 0 ) 
... )

If I try to call the component while passing
  instanceMyTypeMatrix( 2 )
there is a compilation error.
If I try to call the component while passing
  std_logic_vector( instanceMyTypeMatrix( 2 ) ) it compiles but the 
vector
is left totally uninitiallized.

Bug of ghdl or mistake from me?

Regards

Patrick

On Thu, Oct 09, 2008 at 08:28:43PM +0200, patrick.pub@nerim.net wrote:
> type myTypeVector( numberofitems - 1 downto 0 )
>   instanceMyTypeMatrix( 2 )
> there is a compilation error.
> If I try to call the component while passing
>   std_logic_vector( instanceMyTypeMatrix( 2 ) ) it compiles but the vector
> is left totally uninitiallized.
> 
> Bug of ghdl or mistake from me?

Hi,

this looks like a mistake from you but it will be more easier to explain
if you provide a compilable example.  In the above exerpt, the first two
lines are not valid VHDL :-)

Tristan.

>
> this looks like a mistake from you but it will be more easier to explain
> if you provide a compilable example.  In the above exerpt, the first two
> lines are not valid VHDL :-)
>
> Tristan.
>
>
>
In the example below, 3 of the 4 "instanceVector: should be 
uninitialized,
but they are all uninitialized.



library ieee;
use ieee.STD_LOGIC_1164.all, ieee.NUMERIC_STD.all;

package test_utils is

  component one_to_all
    generic (
      size_o : positive);
    port (
      theInput  : in  std_logic;        -- bit for "others"
      theOutput : out std_logic_vector(size_o - 1 downto 0));  -- others
=> theInput
  end component;

end test_utils;

library ieee;
use ieee.STD_LOGIC_1164.all, ieee.NUMERIC_STD.all;
use work.test_utils.one_to_all;

entity one_to_all is

  generic (
    size_o : positive);

  port (
    theInput : in std_logic;
    theOutput : out std_logic_vector( size_o - 1 downto 0 ));

end one_to_all;

architecture arch_one_to_all of one_to_all is

begin  -- arch_one_to_all

  theOutput <= ( others => theInput );

end arch_one_to_all;

library ieee;
use ieee.STD_LOGIC_1164.all, ieee.NUMERIC_STD.all;
use work.test_utils.one_to_all;

entity bench_test is
  generic (
    with_the_cast : boolean := true;
    size_o : positive := 6;
    nbre_of_elements : positive := 3);
end bench_test;

architecture arch_bench_test of bench_test is
  signal counter_int : unsigned( 3 downto 0 ) := "0000";  -- main clk 
counter
  signal counter_max : unsigned( 3 downto 0 ) := "1000";  -- value that
stops the simul

  type myVector is array (size_o - 1 downto 0 ) of std_logic;
  type myMatrix is array (nbre_of_elements downto 0) of myVector;
  signal instanceMatrix : myMatrix;
  signal instanceVector0 : myVector;
  signal instanceVector1 : myVector;
  signal instanceVector2 : myVector;
  signal instanceVector3 : myVector;
begin  -- arch_bench_test

  -- purpose: main process for the demo
  -- type   : sequential
  -- inputs : CLK
  -- outputs: the output of the one_in_all entity
  theClock: process
  begin  -- process theClock
    if counter_int = counter_max then
      wait;
    else
      counter_int <= counter_int + 1;
      wait for 1 ns;
    end if;
  end process theClock;

  ota_instanc : one_to_all generic map (
    size_o => size_o)
    port map (
      theInput  => counter_int(1),
      -- Here if the cast is removed,
      -- error is issued while trying to run ghdl with the -a option :
      -- test.vhdl:xyz:7: no interface for 'theoutput' in association
      theOutput => std_logic_vector(instanceMatrix(1)));

  instanceVector0 <= instanceMatrix(0);
  instanceVector1 <= instanceMatrix(1);
  instanceVector2 <= instanceMatrix(2);
  instanceVector3 <= instanceMatrix(3);
end arch_bench_test;

Hi Patrick,

concerning your question:
      -- Here if the cast is removed,
      -- error is issued while trying to run ghdl with the -a option :
      -- test.vhdl:xyz:7: no interface for 'theoutput' in association
      theOutput => std_logic_vector(instanceMatrix(1)));

ghdl is right: the type of theOutput is std_logic_vector while the
type of instanceMatrix is myVector.  As these are different types, a
type convertion (what you call a cast) is required.

You can avoid this type convertion by declaring MyVector as:

  subtype myvector is std_logic_vector (size_o - 1 downto 0);


I am investigating the other point.

Tristan.

On Wed, Oct 15, 2008 at 10:06:24PM +0200, patrick.pub@nerim.net wrote:
> In the example below, 3 of the 4 "instanceVector: should be uninitialized,
> but they are all uninitialized.

In fact there is a bug in ghdl and in your design:

>       -- Here if the cast is removed,
>       -- error is issued while trying to run ghdl with the -a option :
>       -- test.vhdl:xyz:7: no interface for 'theoutput' in association
>       theOutput => std_logic_vector(instanceMatrix(1)));

Because the mode is out, you should write:
   myVector (theOutput) => instanceMatrix(1)));

Ghdl doesn't catch this error.

Tristan.

Hi

Thanks you to all, now it works while casting to the left side.

The reason I worked like this is the module is a gradient calculator for
video applications that calculates at blanking time 2**N - 2 linear 
values
between A and B. Everyting is configurable via the generic parameters
including the size of input and output.
For many reasons, I wanted i) a matrix definition at the global level 
for
inter modules communications ii) a matrix organized as a vector of 
vectors
inside modules for slicing reasons.
My problem was I can define:
type ... range ( positive , positive ) of ...
but I can not defined ranges hyerarchically
type ... range ( positive ) of ... range ( positive ) of ...
To fix this situation I defined inside architectures some vectors while
using a generic parameter and I defined a "matrix" as vectors of these
vectors using another parameter.

Does the principle of multi dimensional dispatched at different level of 
a
type definition not supported by Ghdl ? by the vhdl in general ? I think
in the vhdl 2008 it is supported.

The second reason is for error tracking. To fit in small cpld's I had to
optimise the calculations while performing serial calculation ( one bit 
at
a time ). The module is divided into sub modules to multiply, add, and
divide by 2**N - 1 ( in fact to multiply by the inverse that is simple 
to
generate in this case ). Re-inventing the wheel have the advantage to
force to cast and avoid erronous connections between sub modules.

Regards

Patrick

On Mon, Oct 27, 2008 at 09:13:11PM +0100, patrick.pub@nerim.net wrote:
> Hi
> 
> Does the principle of multi dimensional dispatched at different level of a
> type definition not supported by Ghdl ? by the vhdl in general ? I think
> in the vhdl 2008 it is supported.

It is supported only by vhdl 2008 (which ghdl doesn't implement yet).

Tristan.