Forum: GHDL Dual simulation VHDL/Verilog

Hy,

I use an IP from open cores (uart16550) written in Verilog, but i don't 
know
Verilog. Then to synthesize it I «packed» the verilog code in VHDL top
component. That work with ISE, I can synthesize it.

But is it possible to simulate it with GHDL ? Or do you know if a free
software can do that ?

Thanks a lot
FabM

But is it possible to simulate it with GHDL ? Or do you know if
  a free software can do that ?

Since you already have xst you can generate a ngc file. This ngc file
can be converted to VHDL using netgen (also part of ISE). You can use
this VHDL to do a simulation in ghdl.

regards,

Mark van Doesburg