Hi, Thank you Eric, Roshan, Brian, Achilleas, Eenrti for your earlier help! I have been going through the verilog code and my observations till now have been that digital downconversion and some amount of decimation are implemented in the FPGA in receive path. I was trying to see if there is any receiver functionality that could be pushed into the FPGA? I wanted to push such a block into the FPGA, that does not use USB bus much to communicate with other receiver blocks and result in USB bus bandwidth gain. I am not clear as to which block would be the best suited for this? Any comments for the same? Also, I am of the opinion that there would be certain blocks which can make smart/efficient use of FPGA features/power as opposed to being implemented as C++ block on general purpose processor. Any help with this one? If there is a common block for both the above questions, then I would like to start with that and implement on the FPGA. Thanks. -Mande.
on 2007-08-01 21:00