Forum: GNU Radio USRP IQ channels flipping during packet transmission

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Ketan M. (Guest)
on 2007-07-21 09:43
(Received via mailing list)
Eric,

Thanks for your quick response. In regards to your comments:

> Are you running one of our standard fpga images, or are you using one that
you have modified?

Yes. I am using the standard FPGA code distributed with GNU Radio
(version
3.0.3 - the latest stable release). I did not write my own verilog code.

> It's seriously unlikely that the contents of the mux register is getting
randomly disturbed.

I am also skeptical that the mux register is randomly changing. However,
I
am very certain that the transmitter is flipping the IQ channels. I have
verified that this is definitely happening at the transmitter. In the
single
antenna transmitter, setting the mux value to (0x0098) prior to sending
a
packet seemed to solve this problem, but not in the 2-antenna case.
Perhaps
some details about my USRP setup and the nature of the bug that I'm
observing might help in understanding this problem.

Below is a boiled down list of method calls which describe how I've set
up
the transmitter chain in our transceiver:
self.u = usrp.sink_c()
self.u.set_nchannels(2)
self.u.set_mux(gru.hexint(0xBA98) )
self.subdev1 = usrp.selected_subdev (self.u, (0,0) )
self.subdev2 = usrp.selected_subdev (self.u, (1,0) )
self.subdev1.set_auto_tr(True)
self.subdev2.set_auto_tr(True)

In our experiments we transmit packets, encoded using our MIMO physical
layer, across the USRP (after appropriate padding). I've observed that
after
some random number of consecutive packets, I receive a packet whose I-Q
channels have been flipped. It took a considerable amount of effort to
diagnose and verify that this was the problem, but I am very certain now
that this is what is happening at the transmitter. I hope that this
might
shed some more light on the problem and help in finding a solution.
Anmar (Guest)
on 2007-07-21 22:11
(Received via mailing list)
Hi Ketan,

I have also noticed the "flipping" , but not when transmitting only when
restarting, the signal flips 90 degree.
but this only happens when using the subdev, when using gr.sig_source_c
this
doesn't happen.
I couldn't see why this only happens with subdev.

Anmar,
--
View this message in context:
http://www.nabble.com/USRP-IQ-channels-flipping-du...
Sent from the GnuRadio mailing list archive at Nabble.com.
Don W. (Guest)
on 2007-07-21 23:31
(Received via mailing list)
> I have also noticed the "flipping" , but not when transmitting only when
> restarting, the signal flips 90 degree.
> but this only happens when using the subdev, when using gr.sig_source_c
> this
> doesn't happen.
> I couldn't see why this only happens with subdev.

I had similar problems during receive.  It appears that one I or Q
sample
was getting lost so the remaining I and Q samples appeared to be
reversed.
The problem only occurred when I was using usrp._read_fpga_reg() to poll
the
rssi register.

-- Don W.
Ketan M. (Guest)
on 2007-07-25 02:30
(Received via mailing list)
After some major debugging, I have found a fix for this problem. To
summarize the problem again: the transmitter seems to flip the IQ
channels at random during packet transmissions, even though I do not
make any changes to mux settings or other USRP settings. In order to
fix this bug, I had to modify the write method inside usrp_basic_tx.
The following has solved the problem:

int
usrp_basic_tx::write (const void *buf, int len, bool *underrun)
{
  int r;

  /*
   * Hydra Patch:
   * Disable transmitter before writing data to USB buffer
   */
  bool enable = disable_tx();

  /* ...... original code for usrp_basic_tx::write ...... */

  /*
   * Hydra Patch:
   * Enable transmitter after writing data to USB buffer
   */
  restore_tx(enable);

  return r;
}

Somehow, by disabling and re-enabling the transmitter around the write
operation, I was able to prevent the transmitter from randomly
flipping the IQ channels. Please let me know if you would like me to
elaborate further on this bug or the fix.

On 7/21/07, Ketan M. <removed_email_address@domain.invalid> wrote:
>
>
> > > 0xBA98. I have noticed however, that at random the transmitter will flip the
> > > transmit a packet; hence, I am certain that the bug is not being caused in
> > that you have modified?  That is, are you writing verilog code?
>
>
> --
> Ketan M.



--
Ketan M.
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